src/mainboard/lattepanda/mu/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <arch/io.h>
   5 #include <baseboard/variants.h>
   6 #include <device/pci_ops.h>
   7 #include <device/pnp_ops.h>
   8 #include <intelpch/espi.h>
   9 #include <soc/pci_devs.h>
  10 #include <superio/ite/common/ite.h>
  11 #include <superio/ite/it8613e/it8613e.h>
  12
  13 #define it8613e_index           (0x2e)
  14 #define it8613e_data            (0x2f)
  15 #define it8613e_ecdata_base     (0xa40)
  16
  17 #define EC_DEV          PNP_DEV(it8613e_index, IT8613E_EC)
  18 #define UART_DEV        PNP_DEV(it8613e_index, IT8613E_SP1)
  19
  20 /*
  21  * IT8613E/LX Super I/O Chip Initialization Settings
  22  */
  23 struct initdata {
  24         u16 reg;
  25         u8  OpAnd;
  26         u8  OpOr;
  27 };
  28
  29 static const struct initdata init_values[] = {
  30         /* Entry ITE SIO configuration */
  31         { it8613e_index, 0x00, 0x87 },
  32         { it8613e_index, 0x00, 0x01 },
  33         { it8613e_index, 0x00, 0x55 },
  34         { it8613e_index, 0x00, 0x55 },
  35         /* Start IT8613E/LX config */
  36         { it8613e_index, 0x00, 0x23 },
  37         { it8613e_data,  0x1f, 0x40 },
  38         /* LDN: 04, EC */
  39         { it8613e_index, 0x00, 0x07 },
  40         { it8613e_data,  0x00, 0x04 },
  41         { it8613e_index, 0x00, 0xf0 },
  42         { it8613e_data,  0x00, 0x00 },
  43         { it8613e_index, 0x00, 0xf1 },
  44         { it8613e_data,  0x00, 0xbf },
  45         { it8613e_index, 0x00, 0xf2 },
  46         { it8613e_data,  0x00, 0x00 },
  47         { it8613e_index, 0x00, 0xf3 },
  48         { it8613e_data,  0x00, 0x00 },
  49         { it8613e_index, 0x00, 0xf4 },
  50         { it8613e_data,  0x00, 0x60 },
  51         { it8613e_index, 0x00, 0xf5 },
  52         { it8613e_data,  0x3f, 0x00 },
  53         { it8613e_index, 0x00, 0xfa },
  54         { it8613e_data,  0x00, 0x00 },
  55         { it8613e_index, 0x00, 0xfb },
  56         { it8613e_data,  0xf3, 0x0c },
  57         /* LDN: 03, Unknown Device */
  58         { it8613e_index, 0x00, 0x07 },
  59         { it8613e_data,  0x00, 0x03 },
  60         { it8613e_index, 0x00, 0xf0 },
  61         { it8613e_data,  0xf7, 0x08 },
  62         { it8613e_index, 0x00, 0x07 },
  63         { it8613e_data,  0x00, 0x07 },
  64         { it8613e_index, 0x00, 0x28 },
  65         { it8613e_data,  0xbf, 0x00 },
  66         { it8613e_index, 0x00, 0x72 },
  67         { it8613e_data,  0xff, 0x00 },
  68         { it8613e_index, 0x00, 0x2c },
  69         { it8613e_data,  0xbf, 0x40 },
  70         /* LDN: 04, EC */
  71         { it8613e_index, 0x00, 0x07 },
  72         { it8613e_data,  0x00, 0x04 },
  73         /* Set IO1 to 0xa40 */
  74         { it8613e_index, 0x00, 0x61 },
  75         { it8613e_data,  0x00, 0x40 },
  76         { it8613e_index, 0x00, 0x60 },
  77         { it8613e_data,  0x00, 0x0a },
  78         /* Set IO2 to 0xa30 */
  79         { it8613e_index, 0x00, 0x62 },
  80         { it8613e_data,  0x00, 0x0a },
  81         { it8613e_index, 0x00, 0x63 },
  82         { it8613e_data,  0x00, 0x30 },
  83         /* Enable the EC Device */
  84         { it8613e_index, 0x00, 0x30 },
  85         { it8613e_data,  0x00, 0x01 },
  86         /* for Environment Controller */
  87         { 0x0a45, 0x00, 0x50 },
  88         { 0x0a46, 0x00, 0xff },
  89         { 0x0a45, 0x00, 0x51 },
  90         { 0x0a46, 0x00, 0x38 },
  91         { 0x0a45, 0x00, 0x00 },
  92         { 0x0a46, 0x00, 0x01 },
  93         { 0x0a45, 0x00, 0x0a },
  94         { 0x0a46, 0x00, 0x64 },
  95         { 0x0a45, 0x00, 0x8e },
  96         { 0x0a46, 0x3f, 0xc0 },
  97         { 0x0a45, 0x00, 0x00 },
  98         { 0x0a46, 0x00, 0x40 },
  99         /* */
 100         { it8613e_index, 0x00, 0x23 },
 101         { it8613e_data,  0xfe, 0x00 },
 102         /* LDN: 07, GPIO */
 103         { it8613e_index, 0x00, 0x07 },
 104         { it8613e_data,  0x00, 0x07 },
 105         { it8613e_index, 0x00, 0x25 },
 106         { it8613e_data,  0x08, 0x00 },
 107         { it8613e_index, 0x00, 0x26 },
 108         { it8613e_data,  0x00, 0x00 },
 109         { it8613e_index, 0x00, 0x27 },
 110         { it8613e_data,  0x00, 0x00 },
 111         { it8613e_index, 0x00, 0x28 },
 112         { it8613e_data,  0x40, 0x00 },
 113         { it8613e_index, 0x00, 0x29 },
 114         { it8613e_data,  0x00, 0x00 },
 115         { it8613e_index, 0x00, 0x71 },
 116         { it8613e_data,  0x00, 0x00 },
 117         { it8613e_index, 0x00, 0x72 },
 118         { it8613e_data,  0x00, 0x90 },
 119         { it8613e_index, 0x00, 0x73 },
 120         { it8613e_data,  0x00, 0x00 },
 121         { it8613e_index, 0x00, 0x2a },
 122         { it8613e_data,  0xdf, 0x00 },
 123         { it8613e_index, 0x00, 0x2b },
 124         { it8613e_data,  0x0f, 0x00 },
 125         { it8613e_index, 0x00, 0x2c },
 126         { it8613e_data,  0x62, 0x00 },
 127         /* LDN: 05, Keyboard */
 128         { it8613e_index, 0x00, 0x07 },
 129         { it8613e_data,  0x00, 0x05 },
 130         /*  Disable the Device */
 131         { it8613e_index, 0x00, 0x30 },
 132         { it8613e_data,  0x00, 0x00 },
 133         /* LDN: 06, Mouse */
 134         { it8613e_index, 0x00, 0x07 },
 135         { it8613e_data,  0x00, 0x06 },
 136         /*  Disable the Device */
 137         { it8613e_index, 0x00, 0x30 },
 138         { it8613e_data,  0x00, 0x00 },
 139         /* LDN: 05, Keyboard */
 140         { it8613e_index, 0x00, 0x07 },
 141         { it8613e_data,  0x00, 0x05 },
 142         { it8613e_index, 0x00, 0xf0 },
 143         { it8613e_data,  0xf7, 0x08 },
 144         /* LDN: 04, EC */
 145         { it8613e_index, 0x00, 0x07 },
 146         { it8613e_data,  0x00, 0x04 },
 147         { it8613e_index, 0x00, 0xf4 },
 148         { it8613e_data,  0x7f, 0x80 },
 149         { it8613e_index, 0x00, 0x70 },
 150         { it8613e_data,  0x00, 0x00 },
 151         /* exit ITE config */
 152         { it8613e_index, 0x00, 0x02 },
 153         { it8613e_data,  0x00, 0x02 },
 154 };
 155
 156 static void sio_init(const struct initdata *table, const size_t count)
 157 {
 158         u8 val;
 159         for (size_t i = 0; i < count; i++) {
 160                 if (table[i].OpAnd != 0) {
 161                         val = inb(table->reg) & table[i].OpAnd;
 162                         val |= table[i].OpOr;
 163                 } else {
 164                         val = table[i].OpOr;
 165                 }
 166
 167                 outb(val, table[i].reg);
 168         }
 169 }
 170
 171 static const struct initdata it8613e_initdata[] = {
 172         { 0x0007, 0x00, IT8613E_GPIO }, /* LDN GPIO */
 173         { 0x0071, 0xf7, 0x00 },         /* ESPI_CLOCK */
 174         { 0x0023, 0xf6, 0x00 },
 175         { 0x002d, 0xfb, (1 << 1) },
 176         { 0x0007, 0x00, IT8613E_CIR },
 177         { 0x0030, 0x00, 0x00 },
 178         { 0x0060, 0x00, 0x00 },
 179         { 0x0061, 0x00, 0x00 },
 180         { 0x0070, 0x00, 0x00 },
 181         { 0x0007, 0x00, IT8613E_EC },   /* LDN EC */
 182         { 0x00f0, 0x00, 0x00 },
 183         { 0x00f1, 0x00, 0xbf },
 184         { 0x00f2, 0x00, 0x00 },
 185         { 0x00f3, 0x00, 0x00 },
 186         { 0x00f4, 0x9f, 0x60 },
 187         { 0x00f5, 0x3f, 0x00 },
 188         { 0x00fa, 0x00, 0x00 },
 189         { 0x00fb, 0xf3, 0x0c },
 190         { 0x0007, 0x00, IT8613E_GPIO }, /* LDN GPIO */
 191         { 0x0026, 0x00, 0x00 },
 192         { 0x0029, 0x00, 0x00 },
 193         { 0x002a, 0x7f, 0x80 },
 194         { 0x002b, 0xbf, 0x00 },
 195 };
 196
 197 static const struct initdata it8613e_ecdata[] = {
 198         { 0x0050, 0x00, 0xff },
 199         { 0x0051, 0x00, 0x15 },
 200         { 0x000a, 0x8f, 0x68 },
 201         { 0x000b, 0x00, 0xc9 },
 202         { 0x000c, 0xf8, 0x07 },
 203         { 0x0013, 0x07, 0x70 },
 204         { 0x0014, 0x7f, 0xc0 },
 205         { 0x005c, 0x7f, 0x80 },
 206         { 0x0056, 0x00, 0x68 },
 207         { 0x0057, 0x00, 0x05 },
 208         { 0x0059, 0x00, 0x00 },
 209         { 0x005c, 0x7f, 0x00 },
 210         { 0x0065, 0x60, 0x04 },
 211         { 0x006d, 0x60, 0x04 },
 212         { 0x0075, 0x60, 0x04 },
 213         { 0x0089, 0x00, 0x30 },
 214         { 0x008a, 0x00, 0x01 },
 215         { 0x008b, 0x00, 0x02 },
 216         { 0x008c, 0x00, 0x01 },
 217         { 0x008e, 0x00, 0x20 },
 218         { 0x0006, 0x00, 0x40 },
 219         { 0x001d, 0x00, 0x14 },
 220         { 0x001e, 0x00, 0x04 },
 221         { 0x0006, 0x00, 0x00 },
 222         { 0x0055, 0x7f, 0x80 },
 223         { 0x0000, 0xbe, 0x41 },
 224         { 0x0000, 0x00, 0x00 },
 225         { 0x0000, 0x00, 0x00 },
 226 };
 227
 228 static void it8613e_init(const u16 p_idx, const u16 p_dat, const struct initdata *table, const size_t count)
 229 {
 230         u8 val;
 231
 232         for (size_t i = 0; i < count; i++) {
 233                 outb(table[i].reg, p_idx);
 234
 235                 if (table[i].OpAnd == 0) {
 236                         val = table[i].OpOr;
 237                 } else {
 238                         val = ((inb(p_dat) & table[i].OpAnd) |
 239                                 table[i].OpOr);
 240                 }
 241
 242                 outb(val, p_dat);
 243         }
 244 }
 245
 246 void bootblock_mainboard_early_init(void)
 247 {
 248         /* fixed io decode of espi */
 249         pci_write_config32(PCH_DEV_ESPI, ESPI_IO_DEC, 0x3c030070);
 250         variant_configure_early_gpio_pads();
 251
 252         /* initial IT8613e/LX from table */
 253         sio_init(init_values, ARRAY_SIZE(init_values));
 254
 255         pnp_enter_conf_state(EC_DEV);
 256         it8613e_init(it8613e_index, it8613e_data,
 257                 it8613e_initdata, ARRAY_SIZE(it8613e_initdata));
 258         pnp_exit_conf_state(EC_DEV);
 259
 260         /* Environment Controller */
 261         it8613e_init(it8613e_ecdata_base + 5, it8613e_ecdata_base + 6,
 262                 it8613e_ecdata, ARRAY_SIZE(it8613e_ecdata));
 263
 264         /* 5VSB_CTRL# disable */
 265         ite_reg_write(EC_DEV, 0xfa, 0);
 266         ite_disable_pme_out(EC_DEV);
 267         ite_ac_resume_southbridge(EC_DEV);
 268
 269         ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
 270 }