src/mainboard/lattepanda/mu/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/alderlake
   4         # FSP configuration
   5         # Sagv Configuration
   6         register "sagv" = "SaGv_Enabled"
   7
   8         # Enable EDP in PortA
   9         register "ddi_portA_config" = "1"
  10         # Enable HDMI in Port B
  11         register "ddi_ports_config" = "{
  12                 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  13         }"
  14
  15         register "s0ix_enable" = "1"
  16
  17         register "serial_io_i2c_mode" = "{
  18                 [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
  19                 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
  20                 [PchSerialIoIndexI2C2] = PchSerialIoPci,
  21                 [PchSerialIoIndexI2C3] = PchSerialIoPci,
  22                 [PchSerialIoIndexI2C4] = PchSerialIoPci,
  23                 [PchSerialIoIndexI2C5] = PchSerialIoPci,
  24         }"
  25
  26         register "serial_io_uart_mode" = "{
  27                 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
  28                 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
  29                 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
  30         }"
  31
  32         # Intel Common SoC Config
  33         register "common_soc_config" = "{
  34                 .i2c[2] = {
  35                         .speed = I2C_SPEED_FAST,
  36                 },
  37                 .i2c[3] = {
  38                         .speed = I2C_SPEED_FAST,
  39                 },
  40                 .i2c[4] = {
  41                         .speed = I2C_SPEED_FAST,
  42                 },
  43                 .i2c[5] = {
  44                         .speed = I2C_SPEED_FAST,
  45                 },
  46         }"
  47
  48         # Configure external V1P05/Vnn/VnnSx Rails
  49         register "ext_fivr_settings" = "{
  50                 .configure_ext_fivr = 1,
  51                 .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
  52                 .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
  53                 .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
  54                 .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
  55                 .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
  56                 .v1p05_voltage_mv = 1050,
  57                 .vnn_voltage_mv = 780,
  58                 .vnn_sx_voltage_mv = 1050,
  59                 .v1p05_icc_max_ma = 500,
  60                 .vnn_icc_max_ma = 500,
  61         }"
  62
  63         device domain 0 on
  64                 device ref igpu on end
  65                 device ref crashlog off end
  66                 device ref xhci on
  67                         register "usb2_ports" = "{
  68                                 [0] = USB2_PORT_MID(OC_SKIP),   // USB3/2 Type A
  69                                 [1] = USB2_PORT_MID(OC_SKIP),   // USB3/2 Type A
  70                                 [2] = USB2_PORT_MID(OC_SKIP),   // USB2 Type A
  71                                 [4] = USB2_PORT_MID(OC_SKIP),   // USB2 Type A
  72                                 [6] = USB2_PORT_MID(OC_SKIP),   // M.2 E 2230
  73                         }"
  74
  75                         register "usb3_ports" = "{
  76                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),// USB3/2 Type A
  77                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),// USB3/2 Type A
  78                         }"
  79                 end
  80                 device ref i2c2 on end
  81                 device ref i2c3 on end
  82                 device ref i2c4 on end
  83                 device ref i2c5 on end
  84                 device ref pcie_rp3 on
  85                         register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
  86                         register "pch_pcie_rp[PCH_RP(3)]" = "{
  87                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED,
  88                                 .pcie_rp_aspm = ASPM_DISABLE,
  89                                 .PcieRpL1Substates = L1_SS_DISABLED,
  90                         }"
  91                         smbios_slot_desc        "SlotTypeM2Socket3" "SlotLengthOther"
  92                                                 "M.2/M 2230 (M2_SSD)" "SlotDataBusWidth1X"
  93                 end
  94                 device ref pcie_rp4 on
  95                         register "pcie_clk_config_flag[3]" = "PCIE_CLK_FREE_RUNNING"
  96                         register "pch_pcie_rp[PCH_RP(4)]" = "{
  97                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED,
  98                                 .pcie_rp_aspm = ASPM_DISABLE,
  99                                 .PcieRpL1Substates = L1_SS_DISABLED,
 100                         }"
 101                         smbios_slot_desc        "SlotTypeM2Socket1_SD" "SlotLengthOther"
 102                                                 "M.2/E 2230 (M2_WIFI)" "SlotDataBusWidth1X"
 103                 end
 104                 device ref pcie_rp7 on          # RTL8111H Ethernet NIC
 105                         register "pcie_clk_config_flag[4]" = "PCIE_CLK_FREE_RUNNING"
 106                         register "pch_pcie_rp[PCH_RP(7)]" = "{
 107                                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
 108                                 .pcie_rp_aspm = ASPM_DISABLE,
 109                                 .PcieRpL1Substates = L1_SS_DISABLED,
 110                         }"
 111                         chip drivers/net
 112                                 # register "wake" = "no link"
 113                                 register "device_index" = "0"
 114                                 register "add_acpi_dma_property" = "true"
 115                                 device pci 00.0 on end
 116                         end
 117                 end
 118                 device ref emmc on
 119                         register "emmc_enable_hs400_mode" = "1"
 120                 end
 121                 device ref hda on
 122                         # HD Audio
 123                         register "pch_hda_dsp_enable" = "1"
 124                         register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
 125                         register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 126                         register "pch_hda_idisp_codec_enable" = "1"
 127                 end
 128                 device ref pch_espi on
 129                         register "gen1_dec" = "0x00fc0201"
 130                         register "gen2_dec" = "0x003c0a01"
 131                         register "gen3_dec" = "0x000c03f1"
 132                         register "gen4_dec" = "0x000c0081"
 133                         chip superio/ite/it8613e
 134                                 device pnp 2e.0 off end
 135                                 device pnp 2e.1 on      # COM 1
 136                                         io 0x60 = 0x3f8
 137                                         irq 0x70 = 4
 138                                         irq 0xf0 = 0x1
 139                                 end
 140                                 device pnp 2e.4 on      # Environment Controller
 141                                         io 0x60 = 0xa40
 142                                         io 0x62 = 0xa30
 143                                         irq 0x70 = 0x00
 144                                 end
 145                                 device pnp 2e.5 off end # Keyboard
 146                                 device pnp 2e.6 off end # Mouse
 147                                 device pnp 2e.7 off end # GPIO
 148                                 device pnp 2e.a off end # CIR
 149                         end
 150                 end
 151         end
 152 end