src/mainboard/lattepanda/mu/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6
   7 /* Pad configuration in ramstage*/
   8 static const struct pad_config gpio_table[] = {
   9         /* CORE_VID0 */
  10         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  11         /* CORE_VID1 */
  12         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  13         /* VR_ALERT_N */
  14         PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
  15         /* SLP_S0_N */
  16         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  17         /* PLTRST_N */
  18         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  19         PAD_CFG_GPO(GPP_B14, 0, PLTRST),
  20
  21         /* ESPI_IO0_EC_R / ESPI_IO0_HDR */
  22         PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
  23         /* ESPI_IO1_EC_R / ESPI_IO1_HDR */
  24         PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
  25         /* ESPI_IO2_EC_R / ESPI_IO2_HDR */
  26         PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
  27         /* ESPI_IO3_EC_R / ESPI_IO3_HDR */
  28         PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
  29         /* ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N */
  30         PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
  31         /* ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N */
  32         PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
  33         /* ESPI_ALERT1_EC_R_N / ESPI_ALERT1_HDR_N */
  34         PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
  35         /* ESPI_CLK_EC_R / ESPI_CLK_HDR */
  36         PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
  37         /* ESPI_RST_EC_R_N / ESPI_RST_HDR_N */
  38         PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
  39
  40         /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
  41         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
  42         /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
  43         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
  44
  45         /* I5  : NC */
  46         PAD_NC(GPP_I5, NONE),
  47         /* I7  : EMMC_CMD ==> EMMC_CMD */
  48         PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
  49         /* I8  : EMMC_DATA0 ==> EMMC_D0 */
  50         PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
  51         /* I9  : EMMC_DATA1 ==> EMMC_D1 */
  52         PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
  53         /* I10 : EMMC_DATA2 ==> EMMC_D2 */
  54         PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
  55         /* I11 : EMMC_DATA3 ==> EMMC_D3 */
  56         PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
  57         /* I12 : EMMC_DATA4 ==> EMMC_D4 */
  58         PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
  59         /* I13 : EMMC_DATA5 ==> EMMC_D5 */
  60         PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
  61         /* I14 : EMMC_DATA6 ==> EMMC_D6 */
  62         PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
  63         /* I15 : EMMC_DATA7 ==> EMMC_D7 */
  64         PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
  65         /* I16 : EMMC_RCLK ==> EMMC_RCLK */
  66         PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
  67         /* I17 : EMMC_CLK ==> EMMC_CLK */
  68         PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
  69         /* I18 : EMMC_RESET# ==> EMMC_RST_L */
  70         PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
  71
  72         /* EDP1_HPD_MIPI_PNL_RST */
  73         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
  74
  75         /* PM_SLP_S0_N */
  76         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  77         /* PLT_RST_N */
  78         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  79         /* PM_SLP_DRAM_N */
  80         PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),
  81         /* CPU_C10_GATE_N_R */
  82         PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
  83
  84         /* DDIB_DP_HDMI_ALS_HDP */
  85         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  86         /* PM_BATLOW_N */
  87         PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
  88         /* AC_PRESENT */
  89         PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
  90         PAD_CFG_GPI_SCI(GPD2, NONE, DEEP, EDGE_SINGLE, INVERT),
  91         /* PWR_BTN_N */
  92         PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
  93         /* SUSB_N_PCH */
  94         PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
  95         /* SUSC_N_PCH */
  96         PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
  97         /* SLP_A_N */
  98         PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
  99         PAD_CFG_GPO(GPD7, 0, PWROK),
 100         /* SUS_CLK */
 101         PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
 102         /* SLP_WLAN_N */
 103         PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
 104         /* SLP_S5_N */
 105         PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
 106         PAD_NC(GPD11, NONE),
 107         PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1),
 108         PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1),
 109         PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1),
 110         PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1),
 111         PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1),
 112
 113         /* SMB_CLK */
 114         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 115         /* SMB_DATA */
 116         PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 117         /* SMB_ALERT_N */
 118         PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1),
 119         /* SML0_CLK */
 120         PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
 121         /* SML1_DATA */
 122         PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
 123         PAD_CFG_TERM_GPO(GPP_C5, 1, DN_20K, PLTRST),
 124         /* SML1_CLK */
 125         PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1),
 126         /* SML1_DATA */
 127         PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1),
 128 };
 129
 130 void variant_configure_gpio_pads(void)
 131 {
 132         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 133 }