src/mainboard/ocp/tiogapass/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <device/pci_def.h>
   5 #include <device/pci_ops.h>
   6 #include <intelblocks/pcr.h>
   7 #include <soc/pci_devs.h>
   8 #include <soc/pcr_ids.h>
   9 #include <superio/aspeed/ast2400/ast2400.h>
  10 #include <superio/aspeed/common/aspeed.h>
  11 #include <tp_pch_gpio.h>
  12
  13 /* these are defined in intelblocks/lpc_lib.h but we can't use them yet */
  14 #define PCR_DMI_LPCIOD 0x2770
  15 #define PCR_DMI_LPCIOE 0x2774
  16 #define ASPEED_CONFIG_INDEX 0x2E
  17 #define ASPEED_CONFIG_DATA 0x2F
  18
  19 static void enable_espi_lpc_io_windows(void)
  20 {
  21         /*
  22          * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports,
  23          * one is connected to debug header (SUART1) and another is used as SOL (SUART2).
  24          * For that end it is wired into BMC virtual port.
  25          */
  26
  27         /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */
  28         pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4));
  29         /* LPC I/O enable: com1 and com2 */
  30         pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1));
  31
  32         /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
  33         pci_s_write_config32(PCH_DEV_LPC, 0x80,
  34                 (1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4));
  35 }
  36
  37 static uint8_t com_to_ast_sio(uint8_t com)
  38 {
  39         switch (com) {
  40         case 0:
  41                 return AST2400_SUART1;
  42         case 1:
  43                 return AST2400_SUART2;
  44         case 2:
  45                 return AST2400_SUART3;
  46         case 4:
  47                 return AST2400_SUART4;
  48         default:
  49                 return AST2400_SUART1;
  50         }
  51 }
  52
  53 void bootblock_mainboard_early_init(void)
  54 {
  55         /* pre-configure Lewisburg PCH GPIO pads */
  56         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
  57
  58         /* Open IO windows */
  59         enable_espi_lpc_io_windows();
  60
  61         /* Configure appropriate physical port of SuperIO chip off BMC */
  62         const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX,
  63                                         com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
  64         aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
  65
  66         /* Port 80h direct to GPIO for LED display */
  67         const pnp_devfn_t gpio_dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO);
  68         aspeed_enable_port80_direct_gpio(gpio_dev, GPIOH);
  69
  70         /* Enable UART function pin */
  71         aspeed_enable_uart_pin(serial_dev);
  72 }