src/mainboard/ocp/tiogapass/devicetree.cb

   1 ## SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 chip soc/intel/xeon_sp/skx
   4
   5         register "pirqa_routing" = "PCH_IRQ11"
   6         register "pirqb_routing" = "PCH_IRQ10"
   7         register "pirqc_routing" = "PCH_IRQ11"
   8         register "pirqd_routing" = "PCH_IRQ11"
   9         register "pirqe_routing" = "PCH_IRQ11"
  10         register "pirqf_routing" = "PCH_IRQ11"
  11         register "pirqg_routing" = "PCH_IRQ11"
  12         register "pirqh_routing" = "PCH_IRQ11"
  13
  14         # configure device interrupt routing
  15         register "ir00_routing" = "0x3210" # IR00, Dev31
  16         register "ir01_routing" = "0x3210" # IR01, Dev30
  17         register "ir02_routing" = "0x3210" # IR02, Dev29
  18         register "ir03_routing" = "0x3210" # IR03, Dev28
  19         register "ir04_routing" = "0x3210" # IR04, Dev27
  20
  21         # configure interrupt polarity control
  22         register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
  23         register "ipc1" = "0x00000000" # IPC1
  24         register "ipc2" = "0x00000000" # IPC2
  25         register "ipc3" = "0x00000000" # IPC3
  26
  27         # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
  28         # FB production turbo_ratio_limit is 0x1f1f1f2022222325
  29         register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
  30         # FB production turbo_ratio_limit_cores is 0x1c1812100c080402
  31         register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
  32
  33         # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
  34         register "pstate_req_ratio" = "0xa"
  35
  36         # configure VTD
  37         register "vtd_support" = "1"
  38         register "coherency_support" = "1"
  39         register "ats_support" = "1"
  40
  41         register "gen2_dec" = "0x000c0ca1" # IPMI KCS
  42
  43         device cpu_cluster 0 on end
  44
  45         device domain 0 on
  46                 device gpio 0 alias pch_gpio on end
  47                 device pci 00.0 on end # Host bridge
  48                 device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers
  49                 device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers
  50                 device pci 04.2 on end # Intel Corporation SkyLake-E CBDMA Registers
  51                 device pci 04.3 on end # Intel Corporation SkyLake-E CBDMA Registers
  52                 device pci 04.4 on end # Intel Corporation SkyLake-E CBDMA Registers
  53                 device pci 04.5 on end # Intel Corporation SkyLake-E CBDMA Registers
  54                 device pci 04.6 on end # Intel Corporation SkyLake-E CBDMA Registers
  55                 device pci 04.7 on end # Intel Corporation SkyLake-E CBDMA Registers
  56                 device pci 05.0 on end # Intel Corporation SkyLake-E MM/Vt-d Configuration Registers
  57                 device pci 05.2 on end # Intel Corporation Device 2025
  58                 device pci 05.4 on end # Intel Corporation Device 2026
  59                 device pci 08.0 on end # Intel Corporation SkyLake-E Ubox Registers
  60                 device pci 08.1 on end # Intel Corporation SkyLake-E Ubox Registers
  61                 device pci 08.2 on end # Intel Corporation SkyLake-E Ubox Registers
  62                 device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0
  63                 device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1
  64                 device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode]
  65                 device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller
  66                 device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1
  67                 device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2
  68                 device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3
  69                 device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
  70                 device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
  71                 device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
  72                 device pci 1f.0 on
  73                         chip drivers/ipmi # BMC KCS
  74                                 device pnp ca2.0 on end
  75                                 use pch_gpio as gpio_dev
  76                                 register "bmc_i2c_address" = "0x20"
  77                                 register "bmc_boot_timeout" = "90"
  78                                 register "post_complete_gpio" = "GPP_B20"
  79                                 register "post_complete_invert" = "1"
  80                         end
  81                         chip drivers/ipmi/ocp # OCP specific IPMI porting
  82                                 device pnp ca2.1 on end
  83                         end
  84                 end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
  85                 device pci 1f.1 hidden end # p2sb
  86                 device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
  87                 device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
  88                 device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller
  89         end
  90 end