src/mainboard/purism/librem_cnl/devicetree.cb

   1 chip soc/intel/cannonlake
   2
   3         # Enable Enhanced Intel SpeedStep
   4         register "eist_enable" = "true"
   5
   6 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
   7         register "SaGv" = "SaGv_Enabled"
   8
   9 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
  10
  11         # Acoustic Noise
  12         register "AcousticNoiseMitigation" = "1"
  13
  14         register "FastPkgCRampDisableIa" = "1"
  15         register "FastPkgCRampDisableGt" = "1"
  16         register "FastPkgCRampDisableSa" = "1"
  17         register "FastPkgCRampDisableFivr" = "1"
  18
  19         register "SlowSlewRateForIa" = "3"      # fast/16
  20         register "SlowSlewRateForGt" = "3"      # fast/16
  21         register "SlowSlewRateForSa" = "3"      # fast/16
  22         register "SlowSlewRateForFivr" = "3"    # fast/16
  23
  24         # Power
  25         register "PchPmSlpS3MinAssert" = "3"    # 50ms
  26         register "PchPmSlpS4MinAssert" = "1"    # 1s
  27         register "PchPmSlpSusMinAssert" = "2"   # 500ms
  28         register "PchPmSlpAMinAssert" = "4"     # 2s
  29
  30         # Thermal
  31         register "tcc_offset" = "10"
  32
  33 # PM Util (soc/intel/cannonlake/pmutil.c)
  34         # GPE configuration
  35         # Note that GPE events called out in ASL code rely on this
  36         # route. i.e. If this route changes then the affected GPE
  37         # offset bits also need to be changed.
  38         # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
  39         register "gpe0_dw0" = "PMC_GPP_C"
  40         register "gpe0_dw1" = "PMC_GPP_D"
  41         register "gpe0_dw2" = "PMC_GPP_E"
  42
  43 # Actual device tree
  44         device domain 0 on
  45                 device ref igpu         on end
  46                 device ref dptf         on
  47                         register "Device4Enable" = "1"
  48                 end
  49                 device ref thermal      on end
  50                 device ref xhci         on end
  51                 device ref sata         on end
  52                 device ref hda          on
  53                         register "PchHdaAudioLinkHda" = "1"
  54                 end
  55                 device ref smbus        on end
  56                 device ref fast_spi     on end
  57         end
  58 end