src/mainboard/razer/blade_stealth_kbl/devicetree.cb

   1 chip soc/intel/skylake
   2         register "deep_s3_enable_ac" = "0"
   3         register "deep_s3_enable_dc" = "0"
   4         register "deep_s5_enable_ac" = "0"
   5         register "deep_s5_enable_dc" = "0"
   6         register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
   7
   8         register "eist_enable" = "true"
   9
  10         # GPE configuration
  11         # Note that GPE events called out in ASL code rely on this
  12         # route. i.e. If this route changes then the affected GPE
  13         # offset bits also need to be changed.
  14         register "gpe0_dw0" = "GPP_C"
  15         register "gpe0_dw1" = "GPP_D"
  16         register "gpe0_dw2" = "GPP_E"
  17
  18         # Disable DPTF
  19         register "dptf_enable" = "0"
  20
  21         # FSP Configuration
  22         register "DspEnable" = "0"
  23         register "IoBufferOwnership" = "0"
  24         register "SkipExtGfxScan" = "1"
  25         register "SaGv" = "SaGv_Enabled"
  26         register "PmConfigSlpS3MinAssert" = "2"         # 50ms
  27         register "PmConfigSlpS4MinAssert" = "1"         # 1s
  28         register "PmConfigSlpSusMinAssert" = "3"        # 500ms
  29         register "PmConfigSlpAMinAssert" = "3"          # 2s
  30
  31         # VR Settings Configuration for 4 Domains
  32         #+----------------+-----------+-----------+-------------+----------+
  33         #| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
  34         #+----------------+-----------+-----------+-------------+----------+
  35         #| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
  36         #| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
  37         #| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
  38         #| Psi3Enable     | 1         | 1         | 1           | 1        |
  39         #| Psi4Enable     | 1         | 1         | 1           | 1        |
  40         #| ImonSlope      | 0         | 0         | 0           | 0        |
  41         #| ImonOffset     | 0         | 0         | 0           | 0        |
  42         #| IccMax         | 6A        | 64A       | 31A         | 31A      |
  43         #| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
  44         #+----------------+-----------+-----------+-------------+----------+
  45         register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
  46                 .vr_config_enable = 1,
  47                 .psi1threshold = VR_CFG_AMP(20),
  48                 .psi2threshold = VR_CFG_AMP(4),
  49                 .psi3threshold = VR_CFG_AMP(1),
  50                 .psi3enable = 0,
  51                 .psi4enable = 0,
  52                 .imon_slope = 0x0,
  53                 .imon_offset = 0x0,
  54                 .icc_max = VR_CFG_AMP(6),
  55                 .voltage_limit = 1520,
  56                 .ac_loadline = 1030,
  57                 .dc_loadline = 1030,
  58         }"
  59
  60         register "domain_vr_config[VR_IA_CORE]" = "{
  61                 .vr_config_enable = 1,
  62                 .psi1threshold = VR_CFG_AMP(20),
  63                 .psi2threshold = VR_CFG_AMP(5),
  64                 .psi3threshold = VR_CFG_AMP(1),
  65                 .psi3enable = 0,
  66                 .psi4enable = 0,
  67                 .imon_slope = 0x0,
  68                 .imon_offset = 0x0,
  69                 .icc_max = VR_CFG_AMP(64),
  70                 .voltage_limit = 1520,
  71                 .ac_loadline = 240,
  72                 .dc_loadline = 240,
  73         }"
  74
  75         register "domain_vr_config[VR_GT_UNSLICED]" = "{
  76                 .vr_config_enable = 1,
  77                 .psi1threshold = VR_CFG_AMP(20),
  78                 .psi2threshold = VR_CFG_AMP(5),
  79                 .psi3threshold = VR_CFG_AMP(1),
  80                 .psi3enable = 0,
  81                 .psi4enable = 0,
  82                 .imon_slope = 0x0,
  83                 .imon_offset = 0x0,
  84                 .icc_max = VR_CFG_AMP(31),
  85                 .voltage_limit = 1520,
  86                 .ac_loadline = 310,
  87                 .dc_loadline = 310,
  88         }"
  89
  90         register "domain_vr_config[VR_GT_SLICED]" = "{
  91                 .vr_config_enable = 1,
  92                 .psi1threshold = VR_CFG_AMP(20),
  93                 .psi2threshold = VR_CFG_AMP(5),
  94                 .psi3threshold = VR_CFG_AMP(1),
  95                 .psi3enable = 0,
  96                 .psi4enable = 0,
  97                 .imon_slope = 0x0,
  98                 .imon_offset = 0x0,
  99                 .icc_max = VR_CFG_AMP(31),
 100                 .voltage_limit = 1520,
 101                 .ac_loadline = 310,
 102                 .dc_loadline = 310,
 103         }"
 104
 105         # PL1 override 25W
 106         # PL2 override 44W
 107         register "power_limits_config" = "{
 108                 .tdp_pl1_override = 25,
 109                 .tdp_pl2_override = 44,
 110         }"
 111
 112         # Send an extra VR mailbox command for the PS4 exit issue
 113         register "SendVrMbxCmd" = "2"
 114
 115         register "SerialIoDevMode" = "{
 116                 [PchSerialIoIndexI2C0]  = PchSerialIoPci,
 117                 [PchSerialIoIndexI2C1]  = PchSerialIoPci,
 118                 [PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
 119                 [PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
 120                 [PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
 121                 [PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 122                 [PchSerialIoIndexSpi0]  = PchSerialIoDisabled,
 123                 [PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
 124                 [PchSerialIoIndexUart0] = PchSerialIoDisabled,
 125                 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
 126                 [PchSerialIoIndexUart2] = PchSerialIoDisabled,
 127         }"
 128
 129         device domain 0 on
 130                 device ref igpu         on
 131                         register "gfx" = "GMA_STATIC_DISPLAYS(0)"
 132
 133                         register "panel_cfg" = "{
 134                                 .up_delay_ms            = 200,
 135                                 .down_delay_ms          = 50,
 136                                 .cycle_delay_ms         = 500,
 137                                 .backlight_on_delay_ms  = 1,
 138                                 .backlight_off_delay_ms = 200,
 139                                 .backlight_pwm_hz       = 200,
 140                         }"
 141                 end
 142                 device ref sa_thermal   on  end
 143                 device ref south_xhci   on  end
 144                 device ref thermal      on  end
 145                 device ref i2c0         on  end
 146                 device ref i2c1         on
 147                         chip drivers/i2c/hid
 148                                 register "generic.hid" = ""PNP0C50""
 149                                 register "generic.desc" = ""Synaptics Touchpad""
 150                                 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E7_IRQ)"
 151                                 register "generic.detect" = "1"
 152                                 register "hid_desc_reg_offset" = "0x20"
 153                                 device i2c 0x2c on end
 154                         end
 155                 end
 156                 device ref heci1        on  end
 157                 device ref uart2        on  end
 158                 device ref pcie_rp1     on  end
 159                 device ref pcie_rp3     on
 160                         register "PcieRpEnable[2]" = "1"
 161                         register "PcieRpLtrEnable[2]" = "1"
 162                 end
 163                 device ref pcie_rp5     on
 164                         register "PcieRpEnable[4]" = "1"
 165                         register "PcieRpLtrEnable[4]" = "1"
 166                         register "PcieRpHotPlug[4]" = "1"
 167                 end
 168                 device ref pcie_rp9     on
 169                         register "PcieRpEnable[8]" = "1"
 170                         register "PcieRpLtrEnable[8]" = "1"
 171                 end
 172                 device ref lpc_espi     on
 173                         register "serirq_mode" = "SERIRQ_CONTINUOUS"
 174
 175                         register "gen1_dec" = "0x000c0681"
 176                         register "gen2_dec" = "0x000c1641"
 177
 178                         chip superio/ite/it8528e
 179                                 device pnp 6e.1 off end
 180                                 device pnp 6e.2 off end
 181                                 device pnp 6e.3 off end
 182                                 device pnp 6e.4 off end
 183                                 device pnp 6e.5 off end
 184                                 device pnp 6e.6 off end
 185                                 device pnp 6e.a off end
 186                                 device pnp 6e.f off end
 187                                 device pnp 6e.10 off end
 188                                 device pnp 6e.11 off end
 189                                 device pnp 6e.12 off end
 190                                 device pnp 6e.13 off end
 191                                 device pnp 6e.14 off end
 192                                 device pnp 6e.17 off end
 193                                 device pnp 6e.18 off end
 194                                 device pnp 6e.19 off end
 195                         end     #superio/ite/it8528e
 196                 end
 197                 device ref hda          on  end
 198                 device ref smbus        on  end
 199                 device ref fast_spi     on  end
 200         end
 201 end