src/mainboard/roda/rk886ex/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <stdint.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_ops.h>
   7 #include <device/pci_ops.h>
   8 #include <device/pci_def.h>
   9 #include <option.h>
  10 #include <northbridge/intel/i945/i945.h>
  11 #include <southbridge/intel/i82801gx/i82801gx.h>
  12 #include <superio/smsc/lpc47n227/lpc47n227.h>
  13
  14 /* Override the default lpc decode ranges */
  15 void mainboard_lpc_decode(void)
  16 {
  17         int lpt_en = 0;
  18
  19         if (get_uint_option("lpt", 0))
  20                 lpt_en = LPT_LPC_EN; /* enable LPT */
  21
  22         pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
  23
  24         pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en);
  25 }
  26
  27 /* This box has two superios, so enabling serial becomes slightly excessive.
  28  * We disable a lot of stuff to make sure that there are no conflicts between
  29  * the two. Also set up the GPIOs from the beginning. This is the "no schematic
  30  * but safe anyways" method.
  31  */
  32
  33 void bootblock_mainboard_early_init(void)
  34 {
  35         const pnp_devfn_t dev = PNP_DEV(0x2e, 0x00);
  36
  37         pnp_enter_conf_state(dev);
  38         pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */
  39         pnp_write_config(dev, 0x02, 0x88); /* UART power on */
  40         pnp_write_config(dev, 0x03, 0x72); /* Floppy */
  41         pnp_write_config(dev, 0x04, 0x01); /* EPP + SPP */
  42         pnp_write_config(dev, 0x14, 0x03); /* Floppy */
  43         pnp_write_config(dev, 0x20, (0x3f0 >> 2)); /* Floppy */
  44         pnp_write_config(dev, 0x23, (0x378 >> 2)); /* PP base */
  45         pnp_write_config(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */
  46         pnp_write_config(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */
  47         pnp_write_config(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */
  48         pnp_write_config(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */
  49         pnp_write_config(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */
  50         /* These are the SMI status registers in the SIO: */
  51         pnp_write_config(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */
  52
  53         pnp_write_config(dev, 0x31, 0x00); /* GPIO1 DIR */
  54         pnp_write_config(dev, 0x32, 0x00); /* GPIO1 POL */
  55         pnp_write_config(dev, 0x33, 0x40); /* GPIO2 DIR */
  56         pnp_write_config(dev, 0x34, 0x00); /* GPIO2 POL */
  57         pnp_write_config(dev, 0x35, 0xff); /* GPIO3 DIR */
  58         pnp_write_config(dev, 0x36, 0x00); /* GPIO3 POL */
  59         pnp_write_config(dev, 0x37, 0xe0); /* GPIO4 DIR */
  60         pnp_write_config(dev, 0x38, 0x00); /* GPIO4 POL */
  61         pnp_write_config(dev, 0x39, 0x80); /* GPIO4 POL */
  62
  63         pnp_exit_conf_state(dev);
  64 }
  65
  66 void mainboard_late_rcba_config(void)
  67 {
  68         /* Device 1f interrupt pin register */
  69         RCBA32(D31IP) = 0x00042220;
  70
  71         /* dev irq route register */
  72         RCBA16(D31IR) = 0x0232;
  73         RCBA16(D30IR) = 0x3246;
  74         RCBA16(D29IR) = 0x0237;
  75         RCBA16(D28IR) = 0x3201;
  76         RCBA16(D27IR) = 0x3216;
  77
  78         /* Disable unused devices */
  79         RCBA32(FD) |= FD_INTLAN;
  80 }
  81
  82 static void init_artec_dongle(void)
  83 {
  84         /* Enable 4MB decoding */
  85         outb(0xf1, 0x88);
  86         outb(0xf4, 0x88);
  87 }
  88
  89 void mainboard_pre_raminit_config(int s3_resume)
  90 {
  91         init_artec_dongle();
  92 }