src/soc/intel/jasperlake/systemagent.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <chip.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <delay.h>
   7 #include <device/pci.h>
   8 #include <device/pci_ops.h>
   9 #include <intelblocks/systemagent.h>
  10 #include <intelblocks/power_limit.h>
  11 #include <soc/iomap.h>
  12 #include <soc/soc_chip.h>
  13 #include <soc/systemagent.h>
  14
  15 /*
  16  * SoC implementation
  17  *
  18  * Add all known fixed memory ranges for Host Controller/Memory
  19  * controller.
  20  */
  21 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
  22 {
  23         static const struct sa_mmio_descriptor soc_fixed_resources[] = {
  24                 { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
  25                                 "PCIEXBAR" },
  26                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  27                 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
  28                 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
  29                 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
  30                 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
  31         };
  32
  33         sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
  34                         ARRAY_SIZE(soc_fixed_resources));
  35
  36         /* Add Vt-d resources if VT-d is enabled */
  37         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
  38                 return;
  39
  40         sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
  41                         ARRAY_SIZE(soc_vtd_resources));
  42 }
  43
  44 /*
  45  * SoC implementation
  46  *
  47  * Perform System Agent Initialization during Ramstage phase.
  48  */
  49 void soc_systemagent_init(struct device *dev)
  50 {
  51         struct soc_power_limits_config *soc_config;
  52         config_t *config;
  53         uint16_t sa_pci_id;
  54         uint8_t tdp;
  55         size_t i = 0;
  56
  57         /* Enable Power Aware Interrupt Routing */
  58         enable_power_aware_intr();
  59
  60         /* Enable BIOS Reset CPL */
  61         enable_bios_reset_cpl();
  62
  63         mdelay(1);
  64         config = config_of_soc();
  65
  66         /* Get System Agent PCI ID */
  67         sa_pci_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xFFFF;
  68
  69         if (sa_pci_id != 0xFFFF) {
  70                 tdp = get_cpu_tdp();
  71
  72                 /* Choose power limits configuration based on the CPU SA PCI ID and
  73                 * CPU TDP value. */
  74                 for (i = 0; i < ARRAY_SIZE(cpuid_to_jsl); i++) {
  75                         if (sa_pci_id == cpuid_to_jsl[i].pci_did &&
  76                                         tdp == cpuid_to_jsl[i].cpu_tdp) {
  77                                 soc_config = &config->power_limits_config[cpuid_to_jsl[i].limits];
  78                                 set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
  79                                 break;
  80                         }
  81                 }
  82         }
  83
  84         if (i == ARRAY_SIZE(cpuid_to_jsl) || sa_pci_id == 0xFFFF) {
  85                 printk(BIOS_ERR, "unknown SA ID: 0x%4x, can't find its TDP."
  86                         " Skipped power limits configuration.\n",
  87                         sa_pci_id);
  88                 return;
  89         }
  90 }