src/soc/intel/meteorlake/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <acpi/acpigen.h>
   6 #include <arch/ioapic.h>
   7 #include <device/mmio.h>
   8 #include <arch/smp/mpspec.h>
   9 #include <console/console.h>
  10 #include <device/device.h>
  11 #include <device/pci_ops.h>
  12 #include <fw_config.h>
  13 #include <intelblocks/cpulib.h>
  14 #include <intelblocks/pmclib.h>
  15 #include <intelblocks/acpi.h>
  16 #include <soc/cpu.h>
  17 #include <soc/iomap.h>
  18 #include <soc/nvs.h>
  19 #include <soc/pci_devs.h>
  20 #include <soc/pm.h>
  21 #include <soc/soc_chip.h>
  22 #include <soc/systemagent.h>
  23 #include <string.h>
  24 #include <types.h>
  25
  26 /*
  27  * List of supported C-states in this processor.
  28  */
  29 enum {
  30         C_STATE_C0,             /* 0 */
  31         C_STATE_C1,             /* 1 */
  32         C_STATE_C1E,            /* 2 */
  33         C_STATE_C6_SHORT_LAT,   /* 3 */
  34         C_STATE_C6_LONG_LAT,    /* 4 */
  35         C_STATE_C7_SHORT_LAT,   /* 5 */
  36         C_STATE_C7_LONG_LAT,    /* 6 */
  37         C_STATE_C7S_SHORT_LAT,  /* 7 */
  38         C_STATE_C7S_LONG_LAT,   /* 8 */
  39         C_STATE_C8,             /* 9 */
  40         C_STATE_C9,             /* 10 */
  41         C_STATE_C10,            /* 11 */
  42         NUM_C_STATES
  43 };
  44
  45 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
  46         [C_STATE_C0] = {},
  47         [C_STATE_C1] = {
  48                 .latency = C1_LATENCY,
  49                 .power = C1_POWER,
  50                 .resource = MWAIT_RES(0, 0),
  51         },
  52         [C_STATE_C1E] = {
  53                 .latency = C1_LATENCY,
  54                 .power = C1_POWER,
  55                 .resource = MWAIT_RES(0, 1),
  56         },
  57         [C_STATE_C6_SHORT_LAT] = {
  58                 .latency = C6_LATENCY,
  59                 .power = C6_POWER,
  60                 .resource = MWAIT_RES(2, 0),
  61         },
  62         [C_STATE_C6_LONG_LAT] = {
  63                 .latency = C6_LATENCY,
  64                 .power = C6_POWER,
  65                 .resource = MWAIT_RES(2, 1),
  66         },
  67         [C_STATE_C7_SHORT_LAT] = {
  68                 .latency = C7_LATENCY,
  69                 .power = C7_POWER,
  70                 .resource = MWAIT_RES(3, 0),
  71         },
  72         [C_STATE_C7_LONG_LAT] = {
  73                 .latency = C7_LATENCY,
  74                 .power = C7_POWER,
  75                 .resource = MWAIT_RES(3, 1),
  76         },
  77         [C_STATE_C7S_SHORT_LAT] = {
  78                 .latency = C7_LATENCY,
  79                 .power = C7_POWER,
  80                 .resource = MWAIT_RES(3, 2),
  81         },
  82         [C_STATE_C7S_LONG_LAT] = {
  83                 .latency = C7_LATENCY,
  84                 .power = C7_POWER,
  85                 .resource = MWAIT_RES(3, 3),
  86         },
  87         [C_STATE_C8] = {
  88                 .latency = C8_LATENCY,
  89                 .power = C8_POWER,
  90                 .resource = MWAIT_RES(4, 0),
  91         },
  92         [C_STATE_C9] = {
  93                 .latency = C9_LATENCY,
  94                 .power = C9_POWER,
  95                 .resource = MWAIT_RES(5, 0),
  96         },
  97         [C_STATE_C10] = {
  98                 .latency = C10_LATENCY,
  99                 .power = C10_POWER,
 100                 .resource = MWAIT_RES(6, 0),
 101         },
 102 };
 103
 104 static int cstate_set_non_s0ix[] = {
 105         C_STATE_C1,
 106         C_STATE_C6_LONG_LAT,
 107         C_STATE_C7S_LONG_LAT
 108 };
 109
 110 static int cstate_set_s0ix[] = {
 111         C_STATE_C1,
 112         C_STATE_C7S_LONG_LAT,
 113         C_STATE_C10
 114 };
 115
 116 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 117 {
 118         static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
 119                                 ARRAY_SIZE(cstate_set_non_s0ix))];
 120         int *set;
 121         int i;
 122
 123         config_t *config = config_of_soc();
 124
 125         int is_s0ix_enable = config->s0ix_enable;
 126
 127         if (is_s0ix_enable) {
 128                 *entries = ARRAY_SIZE(cstate_set_s0ix);
 129                 set = cstate_set_s0ix;
 130         } else {
 131                 *entries = ARRAY_SIZE(cstate_set_non_s0ix);
 132                 set = cstate_set_non_s0ix;
 133         }
 134
 135         for (i = 0; i < *entries; i++) {
 136                 map[i] = cstate_map[set[i]];
 137                 map[i].ctype = i + 1;
 138         }
 139         return map;
 140 }
 141
 142 void soc_power_states_generation(int core_id, int cores_per_package)
 143 {
 144         config_t *config = config_of_soc();
 145
 146         if (config->eist_enable)
 147                 /* Generate P-state tables */
 148                 generate_p_state_entries(core_id, cores_per_package);
 149 }
 150
 151 void soc_fill_fadt(acpi_fadt_t *fadt)
 152 {
 153         const uint16_t pmbase = ACPI_BASE_ADDRESS;
 154
 155         config_t *config = config_of_soc();
 156
 157         fadt->pm_tmr_blk = pmbase + PM1_TMR;
 158         fadt->pm_tmr_len = 4;
 159
 160         fill_fadt_extended_pm_io(fadt);
 161
 162         if (config->s0ix_enable)
 163                 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 164 }
 165
 166 static struct min_sleep_state min_pci_sleep_states[] = {
 167         { SA_DEVFN_ROOT,        ACPI_DEVICE_SLEEP_D3 },
 168         { SA_DEVFN_IGD,         ACPI_DEVICE_SLEEP_D3 },
 169         { PCI_DEVFN_IPU,        ACPI_DEVICE_SLEEP_D3 },
 170         { PCI_DEVFN_TBT0,       ACPI_DEVICE_SLEEP_D3 },
 171         { PCI_DEVFN_TBT1,       ACPI_DEVICE_SLEEP_D3 },
 172         { PCI_DEVFN_TBT2,       ACPI_DEVICE_SLEEP_D3 },
 173         { PCI_DEVFN_TBT3,       ACPI_DEVICE_SLEEP_D3 },
 174         { PCI_DEVFN_GNA,        ACPI_DEVICE_SLEEP_D3 },
 175         { PCI_DEVFN_TCSS_XHCI,  ACPI_DEVICE_SLEEP_D3 },
 176         { PCI_DEVFN_TCSS_XDCI,  ACPI_DEVICE_SLEEP_D3 },
 177         { SA_DEVFN_TCSS_DMA0,   ACPI_DEVICE_SLEEP_D3 },
 178         { SA_DEVFN_TCSS_DMA1,   ACPI_DEVICE_SLEEP_D3 },
 179         { PCI_DEVFN_VMD,        ACPI_DEVICE_SLEEP_D3 },
 180         { PCI_DEVFN_THC0,       ACPI_DEVICE_SLEEP_D3 },
 181         { PCI_DEVFN_THC1,       ACPI_DEVICE_SLEEP_D3 },
 182         { PCH_DEVFN_XHCI,       ACPI_DEVICE_SLEEP_D3 },
 183         { PCI_DEVFN_USBOTG,     ACPI_DEVICE_SLEEP_D3 },
 184         { PCI_DEVFN_SRAM,       ACPI_DEVICE_SLEEP_D3 },
 185         { PCI_DEVFN_CNVI_WIFI,  ACPI_DEVICE_SLEEP_D3 },
 186         { PCI_DEVFN_I2C0,       ACPI_DEVICE_SLEEP_D3 },
 187         { PCI_DEVFN_I2C1,       ACPI_DEVICE_SLEEP_D3 },
 188         { PCI_DEVFN_I2C2,       ACPI_DEVICE_SLEEP_D3 },
 189         { PCI_DEVFN_I2C3,       ACPI_DEVICE_SLEEP_D3 },
 190         { PCH_DEVFN_CSE,        ACPI_DEVICE_SLEEP_D0 },
 191         { PCI_DEVFN_SATA,       ACPI_DEVICE_SLEEP_D3 },
 192         { PCI_DEVFN_I2C4,       ACPI_DEVICE_SLEEP_D3 },
 193         { PCI_DEVFN_I2C5,       ACPI_DEVICE_SLEEP_D3 },
 194         { PCI_DEVFN_UART2,      ACPI_DEVICE_SLEEP_D3 },
 195         { PCI_DEVFN_PCIE1,      ACPI_DEVICE_SLEEP_D0 },
 196         { PCI_DEVFN_PCIE2,      ACPI_DEVICE_SLEEP_D0 },
 197         { PCI_DEVFN_PCIE3,      ACPI_DEVICE_SLEEP_D0 },
 198         { PCI_DEVFN_PCIE4,      ACPI_DEVICE_SLEEP_D0 },
 199         { PCI_DEVFN_PCIE5,      ACPI_DEVICE_SLEEP_D0 },
 200         { PCI_DEVFN_PCIE6,      ACPI_DEVICE_SLEEP_D0 },
 201         { PCI_DEVFN_PCIE7,      ACPI_DEVICE_SLEEP_D0 },
 202         { PCI_DEVFN_PCIE8,      ACPI_DEVICE_SLEEP_D0 },
 203         { PCI_DEVFN_PCIE9,      ACPI_DEVICE_SLEEP_D0 },
 204         { PCI_DEVFN_PCIE10,     ACPI_DEVICE_SLEEP_D0 },
 205         { PCI_DEVFN_PCIE11,     ACPI_DEVICE_SLEEP_D0 },
 206         { PCI_DEVFN_PCIE12,     ACPI_DEVICE_SLEEP_D0 },
 207         { PCI_DEVFN_UART0,      ACPI_DEVICE_SLEEP_D3 },
 208         { PCI_DEVFN_UART1,      ACPI_DEVICE_SLEEP_D3 },
 209         { PCI_DEVFN_GSPI0,      ACPI_DEVICE_SLEEP_D3 },
 210         { PCI_DEVFN_GSPI1,      ACPI_DEVICE_SLEEP_D3 },
 211         { PCI_DEVFN_ESPI,       ACPI_DEVICE_SLEEP_D0 },
 212         { PCH_DEVFN_PMC,        ACPI_DEVICE_SLEEP_D0 },
 213         { PCI_DEVFN_HDA,        ACPI_DEVICE_SLEEP_D0 },
 214         { PCI_DEVFN_SPI,        ACPI_DEVICE_SLEEP_D3 },
 215         { PCI_DEVFN_GBE,        ACPI_DEVICE_SLEEP_D3 },
 216 };
 217
 218 struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size)
 219 {
 220         *size = ARRAY_SIZE(min_pci_sleep_states);
 221         return min_pci_sleep_states;
 222 }
 223
 224 uint32_t soc_read_sci_irq_select(void)
 225 {
 226         return read32p(soc_read_pmc_base() + IRQ_REG);
 227 }
 228
 229 static unsigned long soc_fill_dmar(unsigned long current)
 230 {
 231         unsigned long tmp;
 232         const uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 233         const bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
 234
 235         printk(BIOS_DEBUG, "%s - gfxvtbar:0x%llx  0x%x\n",
 236                 __func__, gfxvtbar, MCHBAR32(GFXVTBAR));
 237         if (is_devfn_enabled(PCI_DEVFN_IGD) && gfxvtbar && gfxvten) {
 238                 tmp = current;
 239                 current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
 240                 current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0);
 241
 242                 acpi_dmar_drhd_fixup(tmp, current);
 243         }
 244
 245         tmp = current;
 246         current += acpi_create_dmar_drhd(current,
 247                         DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE_ADDRESS);
 248         current += acpi_create_dmar_ds_ioapic_from_hw(current,
 249                         IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
 250                         V_P2SB_CFG_IBDF_FUNC);
 251         current += acpi_create_dmar_ds_msi_hpet(current,
 252                         0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
 253                         V_P2SB_CFG_HBDF_FUNC);
 254         acpi_dmar_drhd_fixup(tmp, current);
 255
 256         /* Add RMRR entry */
 257         if (is_devfn_enabled(PCI_DEVFN_IGD) && gfxvtbar && gfxvten) {
 258                 tmp = current;
 259                 current += acpi_create_dmar_rmrr(current, 0,
 260                                 sa_get_gsm_base(), sa_get_tolud_base() - 1);
 261                 current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0);
 262                 acpi_dmar_rmrr_fixup(tmp, current);
 263         }
 264
 265         tmp = current;
 266         current += acpi_create_dmar_satc(current, ATC_REQUIRED, 0);
 267         current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0);
 268         current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IPU, 0);
 269         if (is_devfn_enabled(PCI_DEVFN_VPU))
 270                 current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_VPU, 0);
 271         acpi_dmar_satc_fixup(tmp, current);
 272
 273         return current;
 274 }
 275
 276 unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current,
 277                                    struct acpi_rsdp *rsdp)
 278 {
 279         acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 280
 281         /*
 282          * Create DMAR table only if we have VT-d capability and FSP does not override its
 283          * feature.
 284          */
 285         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
 286             !(MCHBAR32(GFXVTBAR) & VTBAR_ENABLED))
 287                 return current;
 288
 289         printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
 290         acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar);
 291         current += dmar->header.length;
 292         current = acpi_align_current(current);
 293         acpi_add_table(rsdp, dmar);
 294
 295         return current;
 296 }
 297
 298 void soc_fill_gnvs(struct global_nvs *gnvs)
 299 {
 300         config_t *config = config_of_soc();
 301
 302         /* Enable DPTF based on mainboard configuration */
 303         gnvs->dpte = config->dptf_enable;
 304
 305         /* Set USB2/USB3 wake enable bitmaps. */
 306         gnvs->u2we = config->usb2_wake_enable_bitmap;
 307         gnvs->u3we = config->usb3_wake_enable_bitmap;
 308 }
 309
 310 int soc_madt_sci_irq_polarity(int sci)
 311 {
 312         return MP_IRQ_POLARITY_HIGH;
 313 }