src/soc/intel/meteorlake/bootblock/soc_die.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/device.h>
   5 #include <device/pci_ops.h>
   6 #include <intelblocks/fast_spi.h>
   7 #include <intelblocks/gspi.h>
   8 #include <intelblocks/lpc_lib.h>
   9 #include <intelblocks/p2sb.h>
  10 #include <intelblocks/pcr.h>
  11 #include <intelblocks/pmclib.h>
  12 #include <intelblocks/rtc.h>
  13 #include <intelblocks/systemagent.h>
  14 #include <intelblocks/tco.h>
  15 #include <intelblocks/uart.h>
  16 #include <soc/bootblock.h>
  17 #include <soc/espi.h>
  18 #include <soc/iomap.h>
  19 #include <soc/p2sb.h>
  20 #include <soc/pci_devs.h>
  21 #include <soc/pcr_ids.h>
  22 #include <soc/pm.h>
  23
  24 #define PCR_PSF8_TO_SHDW_PMC_REG_BASE   0xA00
  25 #define PCR_PSFX_TO_SHDW_BAR0   0
  26 #define PCR_PSFX_TO_SHDW_BAR1   0x4
  27 #define PCR_PSFX_TO_SHDW_BAR2   0x8
  28 #define PCR_PSFX_TO_SHDW_BAR3   0xC
  29 #define PCR_PSFX_TO_SHDW_BAR4   0x10
  30 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN     0x01
  31 #define PCR_PSFX_T0_SHDW_PCIEN  0x1C
  32
  33 #define PCR_DMI_ACPIBA          0x27B4
  34 #define PCR_DMI_ACPIBDID        0x27B8
  35 #define PCR_DMI_PMBASEA         0x27AC
  36 #define PCR_DMI_PMBASEC         0x27B0
  37
  38 static void soc_die_config_pwrmbase(void)
  39 {
  40         /*
  41          * Assign Resources to PWRMBASE
  42          * Clear BIT 1-2  Command Register
  43          */
  44         pci_and_config16(PCI_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
  45
  46         /* Program PWRM Base */
  47         pci_write_config32(PCI_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
  48
  49         /* Enable Bus Master and MMIO Space */
  50         pci_or_config16(PCI_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
  51
  52         /* Enable PWRM in PMC */
  53         setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
  54 }
  55
  56 static void soc_die_early_iorange_init(void)
  57 {
  58         uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
  59                 LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
  60
  61         /* IO Decode Range */
  62         if (CONFIG(DRIVERS_UART_8250IO))
  63                 lpc_io_setup_comm_a_b();
  64
  65         /* IO Decode Enable */
  66         lpc_enable_fixed_io_ranges(io_enables);
  67
  68         /* Program generic IO Decode Range */
  69         pch_enable_lpc();
  70 }
  71
  72 static void soc_die_early_ip_init(void)
  73 {
  74         /*
  75          * Perform P2SB configuration before any another controller initialization as the
  76          * controller might want to perform PCR settings.
  77          */
  78         p2sb_enable_bar();
  79         p2sb_configure_hpet();
  80
  81         fast_spi_early_init(SPI_BASE_ADDRESS);
  82         gspi_early_bar_init();
  83
  84         /*
  85          * Enabling SoC PMC PWRM Base for accessing
  86          * Global Reset Cause Register.
  87          */
  88         soc_die_config_pwrmbase();
  89 }
  90
  91 static void soc_die_early_sa_init(void)
  92 {
  93         const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
  94                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  95         };
  96
  97         bootblock_systemagent_early_init();
  98
  99         /* Enable MCHBAR early, needed by IOC driver */
 100         sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources));
 101 }
 102
 103 void bootblock_soc_die_early_init(void)
 104 {
 105         /*
 106          * Ensure performing SA related programming including MCHBAR prior to accessing
 107          * IOC driver.
 108          */
 109         soc_die_early_sa_init();
 110
 111         soc_die_early_ip_init();
 112
 113         fast_spi_cache_bios_region();
 114         soc_die_early_iorange_init();
 115         if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
 116                 uart_bootblock_init();
 117 }
 118
 119 static void soc_die_config_acpibase(void)
 120 {
 121         uint32_t pmc_reg_value;
 122         uint32_t pmc_base_reg = PCR_PSF8_TO_SHDW_PMC_REG_BASE;
 123
 124         pmc_reg_value = pcr_read32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
 125
 126         if (pmc_reg_value != 0xffffffff) {
 127                 /* Disable Io Space before changing the address */
 128                 pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
 129                                 ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
 130                 /* Program ABASE in PSF3 PMC space BAR4 */
 131                 pcr_write32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
 132                                 ACPI_BASE_ADDRESS);
 133                 /* Enable IO Space */
 134                 pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
 135                                 ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
 136         }
 137 }
 138
 139 void bootblock_soc_die_init(void)
 140 {
 141         /*
 142          * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
 143          * GPE0_STS, GPE0_EN registers.
 144          */
 145         soc_die_config_acpibase();
 146
 147         /* Set up GPE configuration */
 148         pmc_gpe_init();
 149
 150         enable_rtc_upper_bank();
 151
 152         /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
 153         tco_configure();
 154 }