soc/intel/xeon_sp/spr: Drop microcode constraints
[coreboot2.git] / src / arch / arm / asmlib.h
blob751dd09665e50185e84de1868943392ea7b503d6
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * This file contains arm architecture specific defines
4 * for the different processors.
6 * Adapted from Linux arch/arm/include/assembler.h
8 * Do not include any C declarations in this file - it is included by
9 * assembler source.
13 * WARNING: This file is *only* meant for memcpy.S and friends which were copied
14 * from Linux and require some weird macros. It does unspeakable things like
15 * redefining "push", so do *not* try to turn it into a general assembly macro
16 * file, and keep it out of global include directories.
19 #ifndef __ARM_ASMLIB_H__
20 #define __ARM_ASMLIB_H__
23 * Endian independent macros for shifting bytes within registers.
25 #ifndef __ARMEB__
26 #define pull lsr
27 #define push lsl
28 #define get_byte_0 lsl #0
29 #define get_byte_1 lsr #8
30 #define get_byte_2 lsr #16
31 #define get_byte_3 lsr #24
32 #define put_byte_0 lsl #0
33 #define put_byte_1 lsl #8
34 #define put_byte_2 lsl #16
35 #define put_byte_3 lsl #24
36 #else
37 #define pull lsl
38 #define push lsr
39 #define get_byte_0 lsr #24
40 #define get_byte_1 lsr #16
41 #define get_byte_2 lsr #8
42 #define get_byte_3 lsl #0
43 #define put_byte_0 lsl #24
44 #define put_byte_1 lsl #16
45 #define put_byte_2 lsl #8
46 #define put_byte_3 lsl #0
47 #endif
50 * Data preload for architectures that support it
52 #if __COREBOOT_ARM_ARCH__ >= 5
53 #define PLD(code...) code
54 #else
55 #define PLD(code...)
56 #endif
59 * This can be used to enable code to cacheline align the destination
60 * pointer when bulk writing to memory. Linux doesn't enable this except
61 * for the "Feroceon" processor, so we better just leave it out.
63 #define CALGN(code...)
65 #endif /* __ARM_ASMLIB_H__ */