soc/intel/xeon_sp/spr: Drop microcode constraints
[coreboot2.git] / src / arch / arm / tables.c
blob0c68fc7c515f83836ad818f13d32aee790184d30
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <bootmem.h>
4 #include <boot/tables.h>
5 #include <boot/coreboot_tables.h>
6 #include <symbols.h>
8 void arch_write_tables(uintptr_t coreboot_table)
12 void bootmem_arch_add_ranges(void)
14 bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE);
15 bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables),
16 BM_MEM_RAMSTAGE);
18 if (!CONFIG(COMMON_CBFS_SPI_WRAPPER))
19 return;
20 bootmem_add_range((uintptr_t)_postram_cbfs_cache,
21 REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);
24 void lb_arch_add_records(struct lb_header *header)