src/include/device/dram/ddr3.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /*
   4  * JEDEC Standard No. 21-C
   5  * Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules 2014
   6  * http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf
   7  */
   8
   9 #ifndef DEVICE_DRAM_DDR3L_H
  10 #define DEVICE_DRAM_DDR3L_H
  11
  12 /**
  13  * @file ddr3.h
  14  *
  15  * \brief Utilities for decoding DDR3 SPDs
  16  */
  17
  18 #include <spd.h>
  19 #include <device/dram/common.h>
  20 #include <types.h>
  21
  22 /** Maximum SPD size supported */
  23 #define SPD_SIZE_MAX_DDR3       256
  24
  25 /**
  26  * Convenience definitions for SPD offsets
  27  *
  28  * @{
  29  */
  30 #define SPD_DIMM_MOD_ID1        117
  31 #define SPD_DIMM_MOD_ID2        118
  32 #define SPD_DIMM_SERIAL_NUM     122
  33 #define SPD_DIMM_SERIAL_LEN     4
  34 #define SPD_DIMM_PART_NUM       128
  35 #define SPD_DIMM_PART_LEN       18
  36 /** @} */
  37
  38 /* Byte 3 [3:0]: DDR3 Module type information */
  39 enum spd_dimm_type_ddr3 {
  40         SPD_DDR3_DIMM_TYPE_UNDEFINED            = 0x00,
  41         SPD_DDR3_DIMM_TYPE_RDIMM                = 0x01,
  42         SPD_DDR3_DIMM_TYPE_UDIMM                = 0x02,
  43         SPD_DDR3_DIMM_TYPE_SO_DIMM              = 0x03,
  44         SPD_DDR3_DIMM_TYPE_MICRO_DIMM           = 0x04,
  45         SPD_DDR3_DIMM_TYPE_MINI_RDIMM           = 0x05,
  46         SPD_DDR3_DIMM_TYPE_MINI_UDIMM           = 0x06,
  47         SPD_DDR3_DIMM_TYPE_MINI_CDIMM           = 0x07,
  48         SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM         = 0x08,
  49         SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM         = 0x09,
  50         SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM         = 0x0a,
  51         SPD_DDR3_DIMM_TYPE_LRDIMM               = 0x0b,
  52         SPD_DDR3_DIMM_TYPE_16B_SO_DIMM          = 0x0c,
  53         SPD_DDR3_DIMM_TYPE_32B_SO_DIMM          = 0x0d,
  54         /* Masks to bits 3:0 to give the dimm type */
  55         SPD_DDR3_DIMM_TYPE_MASK                 = 0x0f,
  56 };
  57
  58 /**
  59  * \brief DIMM flags
  60  *
  61  * Characteristic flags for the DIMM, as presented by the SPD
  62  */
  63 union dimm_flags_ddr3_st {
  64         /* The whole point of the union/struct construct is to allow us to clear
  65          * all the bits with one line: flags.raw = 0.
  66          * We do not care how these bits are ordered */
  67         struct {
  68                 /* Indicates if rank 1 of DIMM uses a mirrored pin mapping. See:
  69                  * Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM */
  70                 unsigned int pins_mirrored:1;
  71                 /* Module can work at 1.50V - All DIMMS must be 1.5V operable */
  72                 unsigned int operable_1_50V:1;
  73                 /* Module can work at 1.35V */
  74                 unsigned int operable_1_35V:1;
  75                 /* Module can work at 1.20V */
  76                 unsigned int operable_1_25V:1;
  77                 /* Has an 8-bit bus extension, meaning the DIMM supports ECC */
  78                 unsigned int is_ecc:1;
  79                 /* DLL-Off Mode Support */
  80                 unsigned int dll_off_mode:1;
  81                 /* Indicates a drive strength of RZQ/6 (40 Ohm) is supported */
  82                 unsigned int rzq6_supported:1;
  83                 /* Indicates a drive strength of RZQ/7 (35 Ohm) is supported */
  84                 unsigned int rzq7_supported:1;
  85                 /* Partial Array Self Refresh */
  86                 unsigned int pasr:1;
  87                 /* On-die Thermal Sensor Readout */
  88                 unsigned int odts:1;
  89                 /* Auto Self Refresh */
  90                 unsigned int asr:1;
  91                 /* Extended temperature range supported */
  92                 unsigned int ext_temp_range:1;
  93                 /* Operating at extended temperature requires 2X refresh rate */
  94                 unsigned int ext_temp_refresh:1;
  95                 /* Thermal sensor incorporated */
  96                 unsigned int therm_sensor:1;
  97         };
  98         unsigned int raw;
  99 };
 100
 101 /**
 102  * \brief DIMM characteristics
 103  *
 104  * The characteristics of each DIMM, as presented by the SPD
 105  */
 106 struct dimm_attr_ddr3_st {
 107         enum spd_memory_type dram_type;
 108         enum spd_dimm_type_ddr3 dimm_type;
 109         u16 cas_supported;
 110         /* Flags extracted from SPD */
 111         union dimm_flags_ddr3_st flags;
 112         /* SDRAM width */
 113         u8 width;
 114         /* Number of ranks */
 115         u8 ranks;
 116         /* Number or row address bits */
 117         u8 row_bits;
 118         /* Number or column address bits */
 119         u8 col_bits;
 120         /* Size of module in MiB */
 121         u32 size_mb;
 122         /* Latencies are in units of 1/256 ns */
 123         u32 tCK;
 124         u32 tAA;
 125         u32 tWR;
 126         u32 tRCD;
 127         u32 tRRD;
 128         u32 tRP;
 129         u32 tRAS;
 130         u32 tRC;
 131         u32 tRFC;
 132         u32 tWTR;
 133         u32 tRTP;
 134         u32 tFAW;
 135         u32 tCWL;
 136         u16 tCMD;
 137
 138         u8 reference_card;
 139         /* XMP: Module voltage in mV */
 140         u16 voltage;
 141         /* XMP: max DIMMs per channel supported (1-4) */
 142         u8 dimms_per_channel;
 143         /* Manufacturer ID */
 144         u16 manufacturer_id;
 145         /* ASCII part number - NULL terminated */
 146         u8 part_number[17];
 147         /* Serial number */
 148         u8 serial[SPD_DIMM_SERIAL_LEN];
 149 };
 150
 151 enum ddr3_xmp_profile {
 152         DDR3_XMP_PROFILE_1 = 0,
 153         DDR3_XMP_PROFILE_2 = 1,
 154 };
 155
 156 typedef u8 spd_raw_data[256];
 157
 158 u16 spd_ddr3_calc_crc(u8 *spd, int len);
 159 u16 spd_ddr3_calc_unique_crc(u8 *spd, int len);
 160 int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data);
 161 int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type);
 162 void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm);
 163 int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm,
 164                         spd_raw_data spd,
 165                         enum ddr3_xmp_profile profile);
 166 enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
 167                              const u16 selected_freq,
 168                              const struct dimm_attr_ddr3_st *info);
 169
 170 #endif /* DEVICE_DRAM_DDR3L_H */