soc/intel/xeon_sp/spr: Drop microcode constraints
[coreboot2.git] / src / include / device / dram / ddr5.h
blobff1604a808a4111d0b19198ce0cc16eab7432080
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef DEVICE_DRAM_DDR5_H
4 #define DEVICE_DRAM_DDR5_H
6 /**
7 * @file ddr5.h
9 * \brief Utilities for decoding (LP)DDR5 info
12 #include <device/dram/common.h>
13 #include <types.h>
15 /** Maximum SPD size supported */
16 #define SPD_SIZE_MAX_DDR5 1024
18 /**
19 * Converts DDR5 clock speed in MHz to the standard reported speed in MT/s
21 uint16_t ddr5_speed_mhz_to_reported_mts(uint16_t speed_mhz);
23 #endif /* DEVICE_DRAM_DDR5_H */