soc/intel/xeon_sp/spr: Drop microcode constraints
[coreboot2.git] / src / include / device / dram / rcd.h
blobd0b1f2c031eefcd3a63b0b44fd4ce2d55266bb68
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #ifndef DEVICE_DRAM_RCD_H
4 #define DEVICE_DRAM_RCD_H
6 #include <types.h>
7 #include <device/i2c_simple.h>
8 #include <console/console.h>
10 enum rcw_idx {
11 VEN_ID_L,
12 VEN_ID_H,
13 DEV_ID_L,
14 DEV_ID_H,
15 REV_ID,
16 RES_05,
17 RES_06,
18 RES_07,
19 F0RC00_01,
20 F0RC02_03,
21 F0RC04_05,
22 F0RC06_07,
23 F0RC08_09,
24 F0RC0A_0B,
25 F0RC0C_0D,
26 F0RC0E_0F,
27 F0RC1x,
28 F0RC2x,
29 F0RC3x,
30 F0RC4x,
31 F0RC5x,
32 F0RC6x,
33 F0RC7x,
34 F0RC8x,
35 F0RC9x,
36 F0RCAx,
37 F0RCBx,
38 F0RCCx,
39 F0RCDx,
40 F0RCEx,
41 F0RCFx,
42 RCW_ALL, /* Total num of bytes */
43 RCW_ALL_ALIGNED /* Total num of bytes after aligning to 4B */
46 _Static_assert(RCW_ALL_ALIGNED % sizeof(uint32_t) == 0,
47 "RCW_ALL_ALIGNED is not aligned");
49 /* Write an 8-bit register. Returns the number of written bytes. */
50 int rcd_write_reg(unsigned int bus, uint8_t slave, enum rcw_idx reg,
51 uint8_t data);
53 /* Write 32 bits of memory (i.e., four 8-bit registers, not 1 32-bit register, which would
54 * involve byte swapping). Returns the number of written bytes. */
55 int rcd_write_32b(unsigned int bus, uint8_t slave, enum rcw_idx reg,
56 uint32_t data);
58 /* Dump 32 bytes of RCD onto the screen. */
59 void dump_rcd(unsigned int bus, uint8_t addr);
61 #endif /* DEVICE_DRAM_RCD_H */