soc/intel/xeon_sp/spr: Drop microcode constraints
[coreboot2.git] / src / include / device / pnp_ops.h
blobb57be454a4fc35bc1ff5dad911fe0d466bde081d
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __DEVICE_PNP_OPS_H__
4 #define __DEVICE_PNP_OPS_H__
6 #include <stdint.h>
7 #include <device/pnp.h>
9 #if ENV_PNP_SIMPLE_DEVICE
11 static __always_inline void pnp_write_config(
12 pnp_devfn_t dev, uint8_t reg, uint8_t value)
14 pnp_write_index(dev >> 8, reg, value);
17 static __always_inline uint8_t pnp_read_config(
18 pnp_devfn_t dev, uint8_t reg)
20 return pnp_read_index(dev >> 8, reg);
23 static __always_inline void pnp_unset_and_set_config(
24 pnp_devfn_t dev, uint8_t reg, uint8_t unset, uint8_t set)
26 pnp_unset_and_set_index(dev >> 8, reg, unset, set);
29 static __always_inline
30 void pnp_set_logical_device(pnp_devfn_t dev)
32 unsigned int device = dev & 0xff;
33 pnp_write_config(dev, 0x07, device);
36 static __always_inline
37 void pnp_set_enable(pnp_devfn_t dev, int enable)
39 pnp_write_config(dev, PNP_IDX_EN, enable?0x1:0x0);
42 static __always_inline
43 int pnp_read_enable(pnp_devfn_t dev)
45 return !!pnp_read_config(dev, PNP_IDX_EN);
48 static __always_inline
49 void pnp_set_iobase(pnp_devfn_t dev, unsigned int index, unsigned int iobase)
51 pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
52 pnp_write_config(dev, index + 1, iobase & 0xff);
55 static __always_inline
56 uint16_t pnp_read_iobase(pnp_devfn_t dev, unsigned int index)
58 return ((uint16_t)(pnp_read_config(dev, index)) << 8)
59 | pnp_read_config(dev, index + 1);
62 static __always_inline
63 void pnp_set_irq(pnp_devfn_t dev, unsigned int index, unsigned int irq)
65 pnp_write_config(dev, index, irq);
68 static __always_inline
69 void pnp_set_drq(pnp_devfn_t dev, unsigned int index, unsigned int drq)
71 pnp_write_config(dev, index, drq & 0xff);
74 #endif
76 #endif