src/soc/intel/meteorlake/crashlog.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/bert_storage.h>
   4 #include <console/console.h>
   5 #include <cpu/cpu.h>
   6 #include <cpu/intel/cpu_ids.h>
   7 #include <delay.h>
   8 #include <device/pci_ops.h>
   9 #include <intelblocks/crashlog.h>
  10 #include <intelblocks/pmc_ipc.h>
  11 #include <soc/crashlog.h>
  12 #include <soc/iomap.h>
  13 #include <soc/pci_devs.h>
  14 #include <string.h>
  15
  16 #define CONTROL_INTERFACE_OFFSET        0x5
  17 #define CRASHLOG_PUNIT_STORAGE_OFF_MASK BIT(24)
  18 #define CRASHLOG_RE_ARM_STATUS_MASK     BIT(25)
  19 #define CRASHLOG_CONSUMED_MASK          BIT(31)
  20
  21 /* global crashLog info */
  22 static bool m_pmc_crashLog_support;
  23 static bool m_pmc_crashLog_present;
  24 static bool m_cpu_crashLog_support;
  25 static bool m_cpu_crashLog_present;
  26 static u32 m_pmc_crashLog_size;
  27 static u32 m_cpu_crashLog_size;
  28 static u32 cpu_crash_version;
  29 static pmc_ipc_discovery_buf_t discovery_buf;
  30 static pmc_crashlog_desc_table_t descriptor_table;
  31 static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap;
  32 static cpu_crashlog_discovery_table_t cpu_cl_disc_tab;
  33 static u32 disc_tab_addr;
  34
  35 static u64 get_disc_tab_header(void)
  36 {
  37         return read64((void *)disc_tab_addr);
  38 }
  39
  40 /* Get the SRAM BAR. */
  41 static uintptr_t get_sram_bar(pci_devfn_t sram_devfn)
  42 {
  43         uintptr_t sram_bar;
  44         const struct device *dev;
  45         struct resource *res;
  46
  47         dev = pcidev_path_on_root(sram_devfn);
  48         if (!dev) {
  49                 printk(BIOS_ERR, "device: 0x%x not found!\n", sram_devfn);
  50                 return 0;
  51         }
  52
  53         res = probe_resource(dev, PCI_BASE_ADDRESS_0);
  54         if (!res) {
  55                 printk(BIOS_ERR, "SOC SRAM device not found!\n");
  56                 return 0;
  57         }
  58
  59         /* Get the base address of the resource */
  60         sram_bar = res->base;
  61
  62         return sram_bar;
  63 }
  64
  65 static void configure_sram(const struct device *sram_dev, u32 base_addr)
  66 {
  67         pci_update_config16(sram_dev, PCI_COMMAND, ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY), 0);
  68
  69         /* Program BAR 0 and enable command register memory space decoding */
  70         pci_write_config32(sram_dev, PCI_BASE_ADDRESS_0, base_addr);
  71         pci_or_config16(sram_dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
  72 }
  73
  74 void cl_get_pmc_sram_data(cl_node_t *head)
  75 {
  76         u32 pmc_sram_base = cl_get_cpu_tmp_bar();
  77         u32 ioe_sram_base = get_sram_bar(PCI_DEVFN_IOE_SRAM);
  78         u32 pmc_crashLog_size = cl_get_pmc_record_size();
  79         cl_node_t *cl_cur = head;
  80
  81         if (!pmc_crashLog_size) {
  82                 printk(BIOS_ERR, "No PMC crashlog records\n");
  83                 return;
  84         }
  85
  86         if (!pmc_sram_base) {
  87                 printk(BIOS_ERR, "PMC SRAM base not valid\n");
  88                 return;
  89         }
  90
  91         if (!ioe_sram_base) {
  92                 printk(BIOS_ERR, "IOE SRAM base not valid\n");
  93                 return;
  94         }
  95
  96         configure_sram(PCI_DEV_IOE_SRAM, ioe_sram_base);
  97
  98         if (!cl_pmc_sram_has_mmio_access())
  99                 return;
 100
 101         if (!cl_ioe_sram_has_mmio_access())
 102                 return;
 103
 104         printk(BIOS_DEBUG, "PMC crashLog size : 0x%x\n", pmc_crashLog_size);
 105
 106         /* goto tail node */
 107         while (cl_cur && cl_cur->next) {
 108                 cl_cur = cl_cur->next;
 109         }
 110
 111         /* process crashlog records */
 112         for (int i = 0; i < descriptor_table.numb_regions + 1; i++) {
 113                 u32 sram_base = 0;
 114                 bool pmc_sram = true;
 115                 printk(BIOS_DEBUG, "Region[0x%x].Tag=0x%x offset=0x%x, size=0x%x\n",
 116                                 i,
 117                                 descriptor_table.regions[i].bits.assign_tag,
 118                                 descriptor_table.regions[i].bits.offset,
 119                                 descriptor_table.regions[i].bits.size);
 120
 121                 if (!descriptor_table.regions[i].bits.size)
 122                         continue;
 123
 124                 /*
 125                  * Region with metadata TAG contains information about BDF entry for SOC PMC SRAM
 126                  * and IOE SRAM. We don't need to parse this as we already define BDFs in
 127                  * soc/pci_devs.h for these SRAMs. Also we need to skip this region as it does not
 128                  * contain any crashlog data.
 129                  */
 130                 if (descriptor_table.regions[i].bits.assign_tag ==
 131                                 CRASHLOG_DESCRIPTOR_TABLE_TAG_META) {
 132                         pmc_crashLog_size -= descriptor_table.regions[i].bits.size *
 133                                                 sizeof(u32);
 134                         printk(BIOS_DEBUG, "Found metadata tag. PMC crashlog size adjusted to: 0x%x\n",
 135                                         pmc_crashLog_size);
 136                         continue;
 137                 } else {
 138                         if (descriptor_table.regions[i].bits.assign_tag ==
 139                                         CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC)
 140                                 sram_base = pmc_sram_base;
 141                         else if (descriptor_table.regions[i].bits.assign_tag ==
 142                                         CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE)
 143                                 sram_base = ioe_sram_base;
 144                         else
 145                                 continue;
 146
 147                         cl_node_t *cl_node = malloc_cl_node(descriptor_table.regions[i].bits.size);
 148
 149                         if (!cl_node) {
 150                                 printk(BIOS_DEBUG, "failed to allocate cl_node [region = %d]\n", i);
 151                                 goto pmc_send_re_arm_after_reset;
 152                         }
 153
 154                         if (cl_copy_data_from_sram(sram_base,
 155                                                 descriptor_table.regions[i].bits.offset,
 156                                                 descriptor_table.regions[i].bits.size,
 157                                                 cl_node->data,
 158                                                 i,
 159                                                 pmc_sram)) {
 160                                 cl_cur->next = cl_node;
 161                                 cl_cur = cl_cur->next;
 162                         } else {
 163                                 /* coping data from sram failed */
 164                                 pmc_crashLog_size -= descriptor_table.regions[i].bits.size *
 165                                                                         sizeof(u32);
 166                                 printk(BIOS_DEBUG, "PMC crashlog size adjusted to: 0x%x\n",
 167                                                         pmc_crashLog_size);
 168                                 /* free cl_node */
 169                                 free_cl_node(cl_node);
 170                         }
 171                 }
 172         }
 173
 174         update_new_pmc_crashlog_size(&pmc_crashLog_size);
 175
 176 pmc_send_re_arm_after_reset:
 177         /* when bit 7 of discov cmd resp is set -> bit 2 of size field */
 178         cl_pmc_re_arm_after_reset();
 179
 180         /* Clear the SSRAM region after copying the error log */
 181         cl_pmc_clear();
 182 }
 183
 184 bool pmc_cl_discovery(void)
 185 {
 186         u32 bar_addr = 0, desc_table_addr = 0;
 187
 188         const struct pmc_ipc_buffer req = { 0 };
 189         struct pmc_ipc_buffer res;
 190         uint32_t cmd_reg;
 191         int r;
 192
 193         cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG,
 194                                 PMC_IPC_CMD_ID_CRASHLOG_DISCOVERY,
 195                                 PMC_IPC_CMD_SIZE_SHIFT);
 196         printk(BIOS_DEBUG, "cmd_reg from pmc_make_ipc_cmd %d in %s\n", cmd_reg, __func__);
 197
 198         r = pmc_send_ipc_cmd(cmd_reg, &req, &res);
 199
 200         if (r < 0) {
 201                 printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__);
 202                 return false;
 203         }
 204         discovery_buf.conv_val_64_bits = ((u64)res.buf[1] << 32) | res.buf[0];
 205
 206         if ((discovery_buf.conv_bits64.supported != 1) ||
 207                 (discovery_buf.conv_bits64.discov_mechanism == 0) ||
 208                         (discovery_buf.conv_bits64.crash_dis_sts == 1)) {
 209                 printk(BIOS_INFO, "PCH crashlog feature not supported.\n");
 210                 m_pmc_crashLog_support = false;
 211                 m_pmc_crashLog_size = 0;
 212                 printk(BIOS_DEBUG, "discovery_buf supported: %d, mechanism: %d, CrashDisSts: %d\n",
 213                         discovery_buf.conv_bits64.supported,
 214                         discovery_buf.conv_bits64.discov_mechanism,
 215                         discovery_buf.conv_bits64.crash_dis_sts);
 216                 return false;
 217         }
 218
 219         printk(BIOS_INFO, "PMC crashlog feature is supported.\n");
 220         m_pmc_crashLog_support = true;
 221
 222         /* Program BAR 0 and enable command register memory space decoding */
 223         bar_addr = get_sram_bar(PCI_DEVFN_SRAM);
 224         if (bar_addr == 0) {
 225                 printk(BIOS_ERR, "PCH SRAM not available, crashlog feature can't be enabled.\n");
 226                 return false;
 227         }
 228
 229         configure_sram(PCI_DEV_SRAM, bar_addr);
 230
 231         desc_table_addr = bar_addr + discovery_buf.conv_bits64.desc_tabl_offset;
 232         m_pmc_crashLog_size = pmc_cl_gen_descriptor_table(desc_table_addr,
 233                                                                 &descriptor_table);
 234         printk(BIOS_DEBUG, "PMC CrashLog size in discovery mode: 0x%X\n",
 235                                         m_pmc_crashLog_size);
 236         m_pmc_crashLog_present = m_pmc_crashLog_size > 0;
 237
 238         return true;
 239 }
 240
 241 u32 cl_get_cpu_bar_addr(void)
 242 {
 243         u32 base_addr = 0;
 244         if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) {
 245                 base_addr = pci_read_config32(PCI_DEV_TELEMETRY, PCI_BASE_ADDRESS_0) &
 246                                 ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
 247         } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) {
 248                 base_addr = pci_read_config32(PCI_DEV_TELEMETRY, PCI_BASE_ADDRESS_1) &
 249                                 ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
 250         } else {
 251                 printk(BIOS_ERR, "Invalid TEL_CFG_BAR value %d, discovery failure expected.\n",
 252                         cpu_cl_devsc_cap.discovery_data.fields.t_bir_q);
 253         }
 254
 255         return base_addr;
 256 }
 257
 258 u32 cl_get_cpu_tmp_bar(void)
 259 {
 260         return get_sram_bar(PCI_DEVFN_SRAM);
 261 }
 262
 263 bool  cl_pmc_sram_has_mmio_access(void)
 264 {
 265         if (pci_read_config16(PCI_DEV_SRAM, PCI_VENDOR_ID) == 0xFFFF) {
 266                 printk(BIOS_ERR, "PMC SSRAM PCI device disabled. Can be enabled in device tree.\n");
 267                 return false;
 268         }
 269
 270         return true;
 271 }
 272
 273 bool  cl_ioe_sram_has_mmio_access(void)
 274 {
 275         if (pci_read_config16(PCI_DEV_IOE_SRAM, PCI_VENDOR_ID) == 0xFFFF) {
 276                 printk(BIOS_ERR, "IOE SSRAM PCI device disabled. Can be enabled in device tree.\n");
 277                 return false;
 278         }
 279         return true;
 280 }
 281
 282 static bool cpu_cl_get_capability(tel_crashlog_devsc_cap_t *cl_devsc_cap)
 283 {
 284         cl_devsc_cap->cap_data.data = pci_read_config32(PCI_DEV_TELEMETRY,
 285                                                 TEL_DVSEC_OFFSET + TEL_DVSEC_PCIE_CAP_ID);
 286         if (cl_devsc_cap->cap_data.fields.pcie_cap_id != TELEMETRY_EXTENDED_CAP_ID) {
 287                 printk(BIOS_DEBUG, "Read ID for Telemetry: 0x%x differs from expected: 0x%x\n",
 288                        cl_devsc_cap->cap_data.fields.pcie_cap_id, TELEMETRY_EXTENDED_CAP_ID);
 289                 return false;
 290         }
 291
 292         /* walk through the entries until crashLog entry */
 293         cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(PCI_DEV_TELEMETRY, TEL_DVSEV_ID);
 294         int new_offset = 0;
 295         while (cl_devsc_cap->devsc_data.fields.devsc_id != CRASHLOG_DVSEC_ID) {
 296                 if (cl_devsc_cap->cap_data.fields.next_cap_offset == 0
 297                      || cl_devsc_cap->cap_data.fields.next_cap_offset == 0xFFFF) {
 298                         printk(BIOS_DEBUG, "Read invalid pcie_cap_id value: 0x%x\n",
 299                                cl_devsc_cap->cap_data.fields.pcie_cap_id);
 300                         return false;
 301                 }
 302                 new_offset = cl_devsc_cap->cap_data.fields.next_cap_offset;
 303                 cl_devsc_cap->cap_data.data = pci_read_config32(PCI_DEV_TELEMETRY,
 304                                                 new_offset + TEL_DVSEC_PCIE_CAP_ID);
 305                 cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(PCI_DEV_TELEMETRY,
 306                                                         new_offset + TEL_DVSEV_ID);
 307         }
 308         cpu_crash_version = cl_devsc_cap->devsc_data.fields.devsc_ver;
 309
 310         cl_devsc_cap->discovery_data.data = pci_read_config32(PCI_DEV_TELEMETRY, new_offset
 311                                                 + TEL_DVSEV_DISCOVERY_TABLE_OFFSET);
 312
 313         return true;
 314 }
 315
 316 static u32 get_disc_table_offset(void)
 317 {
 318         u32 offset = cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset;
 319         if (cpu_get_cpuid() >= CPUID_METEORLAKE_B0) {
 320                 offset <<= 3;
 321                 printk(BIOS_DEBUG, "adjusted cpu discovery table offset: 0x%x\n", offset);
 322         }
 323
 324         return offset;
 325 }
 326
 327 static bool is_crashlog_data_valid(u32 dw0)
 328 {
 329         return (dw0 != 0x0 && dw0 != INVALID_CRASHLOG_RECORD);
 330 }
 331
 332 static bool cpu_cl_gen_discovery_table(void)
 333 {
 334         u32 bar_addr = cl_get_cpu_bar_addr();
 335
 336         if (!bar_addr)
 337                 return false;
 338
 339         disc_tab_addr = bar_addr + get_disc_table_offset();
 340
 341         u32 dw0 = read32((u32 *)disc_tab_addr);
 342         if (!is_crashlog_data_valid(dw0))
 343                 return false;
 344
 345         memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t));
 346         cpu_cl_disc_tab.header.data = get_disc_tab_header();
 347         printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer count: 0x%x\n",
 348                 cpu_cl_disc_tab.header.fields.count);
 349
 350         int cur_offset = 0;
 351         for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) {
 352                 cur_offset = 8 + 24 * i;
 353
 354                 dw0 = read32((u32 *)disc_tab_addr + cur_offset);
 355                 if (!is_crashlog_data_valid(dw0))
 356                         continue;
 357
 358                 if (dw0 & CRASHLOG_CONSUMED_MASK) {
 359                         printk(BIOS_DEBUG, "cpu crashlog records already consumed."
 360                                                 "id: 0x%x dw0: 0x%x\n", i, dw0);
 361                         break;
 362                 }
 363
 364                 cpu_cl_disc_tab.buffers[i].data = read64((void *)(disc_tab_addr + cur_offset));
 365                 printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: "
 366                         "0x%x offset: 0x%x\n", i,  cpu_cl_disc_tab.buffers[i].fields.size,
 367                         cpu_cl_disc_tab.buffers[i].fields.offset);
 368                 m_cpu_crashLog_size += cpu_cl_disc_tab.buffers[i].fields.size * sizeof(u32);
 369         }
 370
 371         if (m_cpu_crashLog_size > 0)
 372                 m_cpu_crashLog_present = true;
 373         else
 374                 m_cpu_crashLog_present = false;
 375
 376         return true;
 377 }
 378
 379 bool cpu_cl_discovery(void)
 380 {
 381         memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t));
 382
 383         if (!cpu_cl_get_capability(&cpu_cl_devsc_cap)) {
 384                 printk(BIOS_ERR, "CPU crashlog capability not found.\n");
 385                 m_cpu_crashLog_support = false;
 386                 return false;
 387         }
 388
 389         m_cpu_crashLog_support = true;
 390
 391         if (!cpu_cl_gen_discovery_table()) {
 392                 printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n");
 393                 m_cpu_crashLog_present = false;
 394                 return false;
 395         }
 396
 397         return true;
 398 }
 399
 400 void reset_discovery_buffers(void)
 401 {
 402         memset(&discovery_buf, 0, sizeof(pmc_ipc_discovery_buf_t));
 403         memset(&descriptor_table, 0, sizeof(pmc_crashlog_desc_table_t));
 404         memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t));
 405 }
 406
 407 int cl_get_total_data_size(void)
 408 {
 409         printk(BIOS_DEBUG, "crashlog size:pmc-0x%x, cpu-0x%x\n",
 410                         m_pmc_crashLog_size, m_cpu_crashLog_size);
 411         return m_pmc_crashLog_size + m_cpu_crashLog_size;
 412 }
 413
 414 static u32 get_control_status_interface(void)
 415 {
 416         if (disc_tab_addr)
 417                 return (disc_tab_addr + CONTROL_INTERFACE_OFFSET * sizeof(u32));
 418         return 0;
 419 }
 420
 421 int cpu_cl_clear_data(void)
 422 {
 423         return 0;
 424 }
 425
 426 static bool wait_and_check(u32 bit_mask)
 427 {
 428         u32 stall_cnt = 0;
 429
 430         do {
 431                 cpu_cl_disc_tab.header.data = get_disc_tab_header();
 432                 udelay(CPU_CRASHLOG_WAIT_STALL);
 433                 stall_cnt++;
 434         } while (((cpu_cl_disc_tab.header.data & bit_mask) == 0) &&
 435                         ((stall_cnt * CPU_CRASHLOG_WAIT_STALL) < CPU_CRASHLOG_WAIT_TIMEOUT));
 436
 437         return (cpu_cl_disc_tab.header.data & bit_mask);
 438 }
 439
 440 void cpu_cl_rearm(void)
 441 {
 442         u32 ctrl_sts_intfc_addr = get_control_status_interface();
 443
 444         if (!ctrl_sts_intfc_addr) {
 445                 printk(BIOS_ERR, "CPU crashlog control and status interface address not valid\n");
 446                 return;
 447         }
 448
 449         /* Rearm the CPU crashlog. Crashlog does not get collected if rearming fails */
 450         cl_punit_control_interface_t punit_ctrl_intfc;
 451         memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
 452         punit_ctrl_intfc.fields.set_re_arm = 1;
 453         write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
 454
 455         if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK))
 456                 printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n");
 457         else
 458                 printk(BIOS_DEBUG, "CPU crashlog re_arm asserted\n");
 459 }
 460
 461 void cpu_cl_cleanup(void)
 462 {
 463         /* Perform any SOC specific cleanup after reading the crashlog data from SRAM */
 464         u32 ctrl_sts_intfc_addr = get_control_status_interface();
 465
 466         if (!ctrl_sts_intfc_addr) {
 467                 printk(BIOS_ERR, "CPU crashlog control and status interface address not valid\n");
 468                 return;
 469         }
 470
 471         /* If storage-off is supported, turn off the PUNIT SRAM
 472          * stroage to save power. This clears crashlog records also.
 473          */
 474
 475         if (!cpu_cl_disc_tab.header.fields.storage_off_support) {
 476                 printk(BIOS_INFO, "CPU crashlog storage_off not supported\n");
 477                 return;
 478         }
 479
 480         cl_punit_control_interface_t punit_ctrl_intfc;
 481         memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t));
 482         punit_ctrl_intfc.fields.set_storage_off = 1;
 483         write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data);
 484
 485         if (!wait_and_check(CRASHLOG_PUNIT_STORAGE_OFF_MASK))
 486                 printk(BIOS_ERR, "CPU crashlog storage_off not asserted\n");
 487         else
 488                 printk(BIOS_DEBUG, "CPU crashlog storage_off asserted\n");
 489 }
 490
 491 pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void)
 492 {
 493         return discovery_buf;
 494 }
 495
 496 pmc_crashlog_desc_table_t cl_get_pmc_descriptor_table(void)
 497 {
 498         return descriptor_table;
 499 }
 500
 501 int cl_get_pmc_record_size(void)
 502 {
 503         return m_pmc_crashLog_size;
 504 }
 505
 506 int cl_get_cpu_record_size(void)
 507 {
 508         return m_cpu_crashLog_size;
 509 }
 510
 511 bool cl_cpu_data_present(void)
 512 {
 513         return m_cpu_crashLog_present;
 514 }
 515
 516 bool cl_pmc_data_present(void)
 517 {
 518         return m_pmc_crashLog_present;
 519 }
 520
 521 bool cpu_crashlog_support(void)
 522 {
 523         return m_cpu_crashLog_support;
 524 }
 525
 526 bool pmc_crashlog_support(void)
 527 {
 528         return m_pmc_crashLog_support;
 529 }
 530
 531 void update_new_pmc_crashlog_size(u32 *pmc_crash_size)
 532 {
 533         m_pmc_crashLog_size = *pmc_crash_size;
 534 }
 535
 536 cpu_crashlog_discovery_table_t cl_get_cpu_discovery_table(void)
 537 {
 538         return cpu_cl_disc_tab;
 539 }
 540
 541 void update_new_cpu_crashlog_size(u32 *cpu_crash_size)
 542 {
 543         m_cpu_crashLog_size = *cpu_crash_size;
 544 }