Documentation/mainboard/up/squared/index.md

   1 # Squared
   2
   3 ## Overview
   4 ### Top
   5 ![][overview_top]
   6
   7 ### Bottom
   8 ![][overview_bottom]
   9
  10 * **Legend**
  11         * [BLUE][header_cn16_link]: UART0 / USB connector
  12         * [GREEN][header_gpio_link]: UART1 / GPIO header
  13         * [RED][header_cn22_link]: SPI header
  14         * YELLOW: Indicates pin 1
  15
  16 ## Mainboard components
  17 ### Platform
  18 ```{eval-rst}
  19 +------------------+----------------------------------+
  20 | CPU              | Intel Atom, Celeron, Pentium     |
  21 +------------------+----------------------------------+
  22 | PCH              | Intel Apollo Lake                |
  23 +------------------+----------------------------------+
  24 | EC / Super IO    | N/A                              |
  25 +------------------+----------------------------------+
  26 | Coprocessor      | Intel TXE 3.0                    |
  27 +------------------+----------------------------------+
  28 ```
  29
  30 ### Flash chip
  31 ```{eval-rst}
  32 +---------------------+------------+
  33 | Type                | Value      |
  34 +=====================+============+
  35 | Socketed flash      | no         |
  36 +---------------------+------------+
  37 | Vendor              | Winbond    |
  38 +---------------------+------------+
  39 | Model               | W25Q128FW  |
  40 +---------------------+------------+
  41 | Voltage             | 1.8V       |
  42 +---------------------+------------+
  43 | Size                | 16 MiB     |
  44 +---------------------+------------+
  45 | Package             | SOIC-8     |
  46 +---------------------+------------+
  47 | Write protection    | No         |
  48 +---------------------+------------+
  49 | Internal flashing   | No         |
  50 +---------------------+------------+
  51 | In circuit flashing | Yes        |
  52 +---------------------+------------+
  53 ```
  54
  55 ### Debugging
  56 #### UART0 (CN16)
  57 This connector is located on the **bottom** side (see [here][overview_bottom_link]).
  58 ![][header_cn16]
  59
  60
  61 #### UART1 (GPIO header)
  62 The GPIO header is located on the **bottom** side (see [here][overview_bottom_link]).
  63 ![][header_gpio]
  64
  65 ## Building and flashing coreboot
  66 ### Using the SPI header
  67 The SPI header is located on the **bottom** side (see [here][overview_bottom_link]).
  68 ![][header_cn22]
  69
  70 ### Preparations
  71 In order to build coreboot, it's necessary to extract some files from the vendor firmware. Make sure that you have a fully working dump.
  72 ```bash
  73 [upsquared]$ ls
  74 firmware_vendor.rom
  75 ```
  76
  77 ```bash
  78 [upsquared]$ mkdir extracted && cd extracted
  79 [extracted]$ ifdtool -x ../firmware_vendor.rom
  80 File ../firmware_vendor.rom is 16777216 bytes
  81 Peculiar firmware descriptor, assuming Ibex Peak compatibility.
  82   Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
  83   Flash Region 1 (BIOS): 00001000 - 00efefff
  84   Flash Region 2 (Intel ME): 07fff000 - 00000fff (unused)
  85   Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
  86   Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
  87   Flash Region 5 (Reserved): 00eff000 - 00ffefff
  88   Flash Region 6 (Reserved): 07fff000 - 00000fff (unused)
  89   Flash Region 7 (Reserved): 07fff000 - 00000fff (unused)
  90   Flash Region 8 (EC): 07fff000 - 00000fff (unused)
  91 ```
  92
  93 ```bash
  94 flashregion_0_flashdescriptor.bin
  95 flashregion_1_bios.bin
  96 flashregion_5_reserved.bin
  97 ```
  98
  99 ### Clean up
 100 ```bash
 101 [coreboot]$ make distclean
 102 ```
 103
 104 ### Configuring
 105 ```bash
 106 [coreboot]$ touch .config
 107 [coreboot]$ ./util/scripts/config --enable VENDOR_UP
 108 [coreboot]$ ./util/scripts/config --enable BOARD_UP_SQUARED
 109 [coreboot]$ ./util/scripts/config --enable NEED_IFWI
 110 [coreboot]$ ./util/scripts/config --enable HAVE_IFD_BIN
 111 [coreboot]$ ./util/scripts/config --set-str IFWI_FILE_NAME "<flashregion_1_bios.bin>"
 112 [coreboot]$ ./util/scripts/config --set-str IFD_BIN_PATH "<flashregion_0_flashdescriptor.bin>"
 113 [coreboot]$ make olddefconfig
 114 ```
 115
 116 ### Building
 117 ```bash
 118 [coreboot]$ make
 119 ```
 120
 121 Now you should have a working and ready to use coreboot build at `build/coreboot.rom`.
 122
 123 ### Flashing
 124 ```bash
 125 [coreboot]$ flashrom -p <your_programmer> -w build/coreboot.rom
 126 ```
 127
 128 ## Board status
 129 ### Working
 130 - bootblock, romstage, ramstage
 131 - Serial console UART0, UART1
 132 - SPI flash console
 133 - iGPU init with libgfxinit
 134 - LAN1, LAN2
 135 - USB2, USB3
 136 - HDMI, DisplayPort
 137 - eMMC
 138 - flashing with flashrom externally
 139
 140 ### Work in progress
 141 - Documentation
 142 - ACPI
 143
 144 ### Not working / Known issues
 145 - Generally SeaBIOS works, but it can't find the CBFS region and therefore it can't load seavgabios. This is because of changes at the Apollolake platform.
 146
 147 ### Untested
 148 - GPIO pin header
 149 - 60 pin EXHAT
 150 - Camera interface
 151   - MIPI-CSI2 2-lane (2MP)
 152   - MIPI-CSI2 4-lane (8MP)
 153 - SATA3
 154 - USB3 OTG
 155 - embedded DisplayPort
 156 - M.2 slot
 157 - mini PCIe
 158 - flashing with flashrom internally using Linux
 159
 160
 161 [header_cn16]: header_cn16_10pin_uart0.svg
 162 [header_cn16_link]: #uart0-cn16
 163 [header_cn22]: header_cn22_12pin_spi.svg
 164 [header_cn22_link]: #using-the-spi-header
 165 [header_gpio]: header_40pin_gpio_uart1.svg
 166 [header_gpio_link]: #uart1-gpio-header
 167 [overview_top]: top.jpg
 168 [overview_bottom]: bottom.jpg
 169 [overview_bottom_link]: #bottom