payloads/libpayload/drivers/serial/ipq40xx.c

   1 /*
   2  * Copyright (c) 2010-2012, 2014, 2016, The Linux Foundation.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above
  11  *       copyright notice, this list of conditions and the following
  12  *       disclaimer in the documentation and/or other materials provided
  13  *       with the distribution.
  14  *     * Neither the name of The Linux Foundation nor the names of its
  15  *       contributors may be used to endorse or promote products derived
  16  *       from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  19  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  25  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  26  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  27  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  28  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include <libpayload.h>
  32
  33 #define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
  34
  35 enum MSM_BOOT_UART_DM_PARITY_MODE {
  36         MSM_BOOT_UART_DM_NO_PARITY,
  37         MSM_BOOT_UART_DM_ODD_PARITY,
  38         MSM_BOOT_UART_DM_EVEN_PARITY,
  39         MSM_BOOT_UART_DM_SPACE_PARITY
  40 };
  41
  42 /* UART Stop Bit Length */
  43 enum MSM_BOOT_UART_DM_STOP_BIT_LEN {
  44         MSM_BOOT_UART_DM_SBL_9_16,
  45         MSM_BOOT_UART_DM_SBL_1,
  46         MSM_BOOT_UART_DM_SBL_1_9_16,
  47         MSM_BOOT_UART_DM_SBL_2
  48 };
  49
  50 /* UART Bits per Char */
  51 enum MSM_BOOT_UART_DM_BITS_PER_CHAR {
  52         MSM_BOOT_UART_DM_5_BPS,
  53         MSM_BOOT_UART_DM_6_BPS,
  54         MSM_BOOT_UART_DM_7_BPS,
  55         MSM_BOOT_UART_DM_8_BPS
  56 };
  57
  58 /* 8-N-1 Configuration */
  59 #define MSM_BOOT_UART_DM_8_N_1_MODE     (MSM_BOOT_UART_DM_NO_PARITY | \
  60                                          (MSM_BOOT_UART_DM_SBL_1 << 2) | \
  61                                          (MSM_BOOT_UART_DM_8_BPS << 4))
  62
  63 /* UART_DM Registers */
  64
  65 /* UART Operational Mode Register */
  66 #define MSM_BOOT_UART_DM_MR1(base)              ((base) + 0x00)
  67 #define MSM_BOOT_UART_DM_MR2(base)              ((base) + 0x04)
  68 #define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF    (1 << 8)
  69 #define MSM_BOOT_UART_DM_LOOPBACK               (1 << 7)
  70
  71 #define PERIPH_BLK_BLSP                 1
  72
  73 /* UART Clock Selection Register */
  74 #if PERIPH_BLK_BLSP
  75 #define MSM_BOOT_UART_DM_CSR(base)              ((base) + 0xA0)
  76 #else
  77 #define MSM_BOOT_UART_DM_CSR(base)              ((base) + 0x08)
  78 #endif
  79
  80 /* UART DM TX FIFO Registers - 4 */
  81 #if PERIPH_BLK_BLSP
  82 #define MSM_BOOT_UART_DM_TF(base, x)            ((base) + 0x100+(4*(x)))
  83 #else
  84 #define MSM_BOOT_UART_DM_TF(base, x)            ((base) + 0x70+(4*(x)))
  85 #endif
  86
  87 /* UART Command Register */
  88 #if PERIPH_BLK_BLSP
  89 #define MSM_BOOT_UART_DM_CR(base)               ((base) + 0xA8)
  90 #else
  91 #define MSM_BOOT_UART_DM_CR(base)               ((base) + 0x10)
  92 #endif
  93 #define MSM_BOOT_UART_DM_CR_RX_ENABLE           (1 << 0)
  94 #define MSM_BOOT_UART_DM_CR_RX_DISABLE          (1 << 1)
  95 #define MSM_BOOT_UART_DM_CR_TX_ENABLE           (1 << 2)
  96 #define MSM_BOOT_UART_DM_CR_TX_DISABLE          (1 << 3)
  97
  98 /* UART Channel Command */
  99 #define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)       ((x & 0x0f) << 4)
 100 #define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x)       ((x >> 4) << 11)
 101 #define MSM_BOOT_UART_DM_CR_CH_CMD(x)           \
 102         (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
 103 #define MSM_BOOT_UART_DM_CMD_NULL               MSM_BOOT_UART_DM_CR_CH_CMD(0)
 104 #define MSM_BOOT_UART_DM_CMD_RESET_RX           MSM_BOOT_UART_DM_CR_CH_CMD(1)
 105 #define MSM_BOOT_UART_DM_CMD_RESET_TX           MSM_BOOT_UART_DM_CR_CH_CMD(2)
 106 #define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT     MSM_BOOT_UART_DM_CR_CH_CMD(3)
 107 #define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT    MSM_BOOT_UART_DM_CR_CH_CMD(4)
 108 #define MSM_BOOT_UART_DM_CMD_START_BRK          MSM_BOOT_UART_DM_CR_CH_CMD(5)
 109 #define MSM_BOOT_UART_DM_CMD_STOP_BRK           MSM_BOOT_UART_DM_CR_CH_CMD(6)
 110 #define MSM_BOOT_UART_DM_CMD_RES_CTS_N          MSM_BOOT_UART_DM_CR_CH_CMD(7)
 111 #define MSM_BOOT_UART_DM_CMD_RES_STALE_INT      MSM_BOOT_UART_DM_CR_CH_CMD(8)
 112 #define MSM_BOOT_UART_DM_CMD_PACKET_MODE        MSM_BOOT_UART_DM_CR_CH_CMD(9)
 113 #define MSM_BOOT_UART_DM_CMD_MODE_RESET         MSM_BOOT_UART_DM_CR_CH_CMD(C)
 114 #define MSM_BOOT_UART_DM_CMD_SET_RFR_N          MSM_BOOT_UART_DM_CR_CH_CMD(D)
 115 #define MSM_BOOT_UART_DM_CMD_RES_RFR_N          MSM_BOOT_UART_DM_CR_CH_CMD(E)
 116 #define MSM_BOOT_UART_DM_CMD_RES_TX_ERR         MSM_BOOT_UART_DM_CR_CH_CMD(10)
 117 #define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE        MSM_BOOT_UART_DM_CR_CH_CMD(11)
 118 #define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT    MSM_BOOT_UART_DM_CR_CH_CMD(12)
 119 #define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT     MSM_BOOT_UART_DM_CR_CH_CMD(13)
 120 #define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT    MSM_BOOT_UART_DM_CR_CH_CMD(14)
 121
 122 /*UART General Command */
 123 #define MSM_UART_DM_CR_GENERAL_CMD(x)           ((x) << 8)
 124
 125 #define MSM_BOOT_UART_DM_GCMD_NULL              MSM_UART_DM_CR_GENERAL_CMD(0)
 126 #define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN        MSM_UART_DM_CR_GENERAL_CMD(1)
 127 #define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS       MSM_UART_DM_CR_GENERAL_CMD(2)
 128 #define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT    MSM_UART_DM_CR_GENERAL_CMD(3)
 129 #define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE    MSM_UART_DM_CR_GENERAL_CMD(4)
 130 #define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT     MSM_UART_DM_CR_GENERAL_CMD(5)
 131 #define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT     MSM_UART_DM_CR_GENERAL_CMD(6)
 132
 133 /* UART Interrupt Mask Register */
 134 #if PERIPH_BLK_BLSP
 135 #define MSM_BOOT_UART_DM_IMR(base)              ((base) + 0xB0)
 136 #else
 137 #define MSM_BOOT_UART_DM_IMR(base)              ((base) + 0x14)
 138 #endif
 139
 140 #define MSM_BOOT_UART_DM_TXLEV                  (1 << 0)
 141 #define MSM_BOOT_UART_DM_RXHUNT                 (1 << 1)
 142 #define MSM_BOOT_UART_DM_RXBRK_CHNG             (1 << 2)
 143 #define MSM_BOOT_UART_DM_RXSTALE                (1 << 3)
 144 #define MSM_BOOT_UART_DM_RXLEV                  (1 << 4)
 145 #define MSM_BOOT_UART_DM_DELTA_CTS              (1 << 5)
 146 #define MSM_BOOT_UART_DM_CURRENT_CTS            (1 << 6)
 147 #define MSM_BOOT_UART_DM_TX_READY               (1 << 7)
 148 #define MSM_BOOT_UART_DM_TX_ERROR               (1 << 8)
 149 #define MSM_BOOT_UART_DM_TX_DONE                (1 << 9)
 150 #define MSM_BOOT_UART_DM_RXBREAK_START          (1 << 10)
 151 #define MSM_BOOT_UART_DM_RXBREAK_END            (1 << 11)
 152 #define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ      (1 << 12)
 153
 154 #define MSM_BOOT_UART_DM_IMR_ENABLED    (MSM_BOOT_UART_DM_TX_READY |    \
 155                                          MSM_BOOT_UART_DM_TXLEV |       \
 156                                          MSM_BOOT_UART_DM_RXSTALE)
 157
 158 /* UART Interrupt Programming Register */
 159 #define MSM_BOOT_UART_DM_IPR(base)              ((base) + 0x18)
 160 #define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB      0x0f
 161 #define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB      0       /* Not used currently */
 162
 163 /* UART Transmit/Receive FIFO Watermark Register */
 164 #define MSM_BOOT_UART_DM_TFWR(base)             ((base) + 0x1C)
 165 /* Interrupt is generated when FIFO level is less than or equal to this value */
 166 #define MSM_BOOT_UART_DM_TFW_VALUE              0
 167
 168 #define MSM_BOOT_UART_DM_RFWR(base)             ((base) + 0x20)
 169 /*Interrupt generated when no of words in RX FIFO is greater than this value */
 170 #define MSM_BOOT_UART_DM_RFW_VALUE              0
 171
 172 /* UART Hunt Character Register */
 173 #define MSM_BOOT_UART_DM_HCR(base)              ((base) + 0x24)
 174
 175 /* Used for RX transfer initialization */
 176 #define MSM_BOOT_UART_DM_DMRX(base)             ((base) + 0x34)
 177
 178 /* Default DMRX value - any value bigger than FIFO size would be fine */
 179 #define MSM_BOOT_UART_DM_DMRX_DEF_VALUE         0x220
 180
 181 /* Register to enable IRDA function */
 182 #if PERIPH_BLK_BLSP
 183 #define MSM_BOOT_UART_DM_IRDA(base)             ((base) + 0xB8)
 184 #else
 185 #define MSM_BOOT_UART_DM_IRDA(base)             ((base) + 0x38)
 186 #endif
 187
 188 /* UART Data Mover Enable Register */
 189 #define MSM_BOOT_UART_DM_DMEN(base)             ((base) + 0x3C)
 190
 191 /* Number of characters for Transmission */
 192 #define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040)
 193
 194 /* UART RX FIFO Base Address */
 195 #define MSM_BOOT_UART_DM_BADR(base)             ((base) + 0x44)
 196
 197 /* UART Status Register */
 198 #if PERIPH_BLK_BLSP
 199 #define MSM_BOOT_UART_DM_SR(base)               ((base) + 0x0A4)
 200 #else
 201 #define MSM_BOOT_UART_DM_SR(base)               ((base) + 0x008)
 202 #endif
 203 #define MSM_BOOT_UART_DM_SR_RXRDY               (1 << 0)
 204 #define MSM_BOOT_UART_DM_SR_RXFULL              (1 << 1)
 205 #define MSM_BOOT_UART_DM_SR_TXRDY               (1 << 2)
 206 #define MSM_BOOT_UART_DM_SR_TXEMT               (1 << 3)
 207 #define MSM_BOOT_UART_DM_SR_UART_OVERRUN        (1 << 4)
 208 #define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR       (1 << 5)
 209 #define MSM_BOOT_UART_DM_RX_BREAK               (1 << 6)
 210 #define MSM_BOOT_UART_DM_HUNT_CHAR              (1 << 7)
 211 #define MSM_BOOT_UART_DM_RX_BRK_START_LAST      (1 << 8)
 212
 213 /* UART Receive FIFO Registers - 4 in numbers */
 214 #if PERIPH_BLK_BLSP
 215 #define MSM_BOOT_UART_DM_RF(base, x)            ((base) + 0x140 + (4*(x)))
 216 #else
 217 #define MSM_BOOT_UART_DM_RF(base, x)            ((base) + 0x70 + (4*(x)))
 218 #endif
 219
 220 /* UART Masked Interrupt Status Register */
 221 #if PERIPH_BLK_BLSP
 222 #define MSM_BOOT_UART_DM_MISR(base)             ((base) + 0xAC)
 223 #else
 224 #define MSM_BOOT_UART_DM_MISR(base)             ((base) + 0x10)
 225 #endif
 226
 227 /* UART Interrupt Status Register */
 228 #if PERIPH_BLK_BLSP
 229 #define MSM_BOOT_UART_DM_ISR(base)              ((base) + 0xB4)
 230 #else
 231 #define MSM_BOOT_UART_DM_ISR(base)              ((base) + 0x14)
 232 #endif
 233
 234 /* Number of characters received since the end of last RX transfer */
 235 #if PERIPH_BLK_BLSP
 236 #define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)  ((base) + 0xBC)
 237 #else
 238 #define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base)  ((base) + 0x38)
 239 #endif
 240
 241 /* UART TX FIFO Status Register */
 242 #define MSM_BOOT_UART_DM_TXFS(base)             ((base) + 0x4C)
 243 #define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x)      \
 244                 MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
 245 #define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x)      \
 246                 MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
 247 #define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x)      \
 248                 MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
 249 #define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x)    \
 250                 MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
 251
 252 /* UART RX FIFO Status Register */
 253 #define MSM_BOOT_UART_DM_RXFS(base)             ((base) + 0x50)
 254 #define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x)      \
 255                 MSM_BOOT_UART_DM_EXTR_BITS(x, 0, 6)
 256 #define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x)      \
 257                 MSM_BOOT_UART_DM_EXTR_BITS(x, 14, 31)
 258 #define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x)      \
 259                 MSM_BOOT_UART_DM_EXTR_BITS(x, 7, 9)
 260 #define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x)    \
 261                 MSM_BOOT_UART_DM_EXTR_BITS(x, 10, 13)
 262
 263 /* Macros for Common Errors */
 264 #define MSM_BOOT_UART_DM_E_SUCCESS              0
 265 #define MSM_BOOT_UART_DM_E_FAILURE              1
 266 #define MSM_BOOT_UART_DM_E_TIMEOUT              2
 267 #define MSM_BOOT_UART_DM_E_INVAL                3
 268 #define MSM_BOOT_UART_DM_E_MALLOC_FAIL          4
 269 #define MSM_BOOT_UART_DM_E_RX_NOT_READY         5
 270
 271 #define UART1_DM_BASE                           ((void *)0x078af000)
 272 #define UART2_DM_BASE                           ((void *)0x078b0000)
 273
 274 enum {
 275         BLSP1_UART1,
 276         BLSP1_UART2,
 277 };
 278
 279 #define FIFO_DATA_SIZE  4
 280
 281 typedef struct {
 282         void *uart_dm_base;
 283         unsigned blsp_uart;
 284 } uart_params_t;
 285
 286 /*
 287  * All constants lifted from u-boot's
 288  * board/qcom/ipq40xx_cdp/ipq40xx_board_param.h
 289  */
 290 static const uart_params_t uart_board_param = {
 291         .uart_dm_base = UART1_DM_BASE,
 292         .blsp_uart = BLSP1_UART1,
 293 };
 294
 295 #define write32(addr, val)              writel(val, addr)
 296 #define read32(addr)                    readl(addr)
 297 /**
 298  * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer
 299  * @uart_dm_base: UART controller base address
 300  */
 301 static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base)
 302 {
 303         /* Reset receiver */
 304         write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
 305                 MSM_BOOT_UART_DM_CMD_RESET_RX);
 306
 307         /* Enable receiver */
 308         write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
 309                 MSM_BOOT_UART_DM_CR_RX_ENABLE);
 310         write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base),
 311                 MSM_BOOT_UART_DM_DMRX_DEF_VALUE);
 312
 313         /* Clear stale event */
 314         write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
 315                 MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
 316
 317         /* Enable stale event */
 318         write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
 319                 MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT);
 320
 321         return MSM_BOOT_UART_DM_E_SUCCESS;
 322 }
 323
 324 static unsigned int msm_boot_uart_dm_init(void  *uart_dm_base);
 325
 326 /* Received data is valid or not */
 327 static int valid_data = 0;
 328
 329 /* Received data */
 330 static unsigned int word = 0;
 331
 332 /**
 333  * msm_boot_uart_dm_read - reads a word from the RX FIFO.
 334  * @data: location where the read data is stored
 335  * @count: no of valid data in the FIFO
 336  * @wait: indicates blocking call or not blocking call
 337  *
 338  * Reads a word from the RX FIFO. If no data is available blocks if
 339  * @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY.
 340  */
 341 static unsigned int
 342 msm_boot_uart_dm_read(unsigned int *data, int *count, int wait)
 343 {
 344         static int total_rx_data = 0;
 345         static int rx_data_read = 0;
 346         void *base;
 347         uint32_t status_reg;
 348
 349         base = uart_board_param.uart_dm_base;
 350
 351         if (data == NULL)
 352                 return MSM_BOOT_UART_DM_E_INVAL;
 353
 354         status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
 355
 356         /* Check for DM_RXSTALE for RX transfer to finish */
 357         while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) {
 358                 status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
 359                 if (!wait)
 360                         return MSM_BOOT_UART_DM_E_RX_NOT_READY;
 361         }
 362
 363         /* Check for Overrun error. We'll just reset Error Status */
 364         if (readl(MSM_BOOT_UART_DM_SR(base)) &
 365                         MSM_BOOT_UART_DM_SR_UART_OVERRUN) {
 366                 writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
 367                         MSM_BOOT_UART_DM_CR(base));
 368                 total_rx_data = rx_data_read = 0;
 369                 msm_boot_uart_dm_init(base);
 370                 return MSM_BOOT_UART_DM_E_RX_NOT_READY;
 371         }
 372
 373         /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */
 374         if (total_rx_data == 0)
 375                 total_rx_data =  readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base));
 376
 377         /* Data available in FIFO; read a word. */
 378         *data = readl(MSM_BOOT_UART_DM_RF(base, 0));
 379
 380         /* WAR for http://prism/CR/548280 */
 381         if (*data == 0)
 382                 return MSM_BOOT_UART_DM_E_RX_NOT_READY;
 383
 384         /* increment the total count of chars we've read so far */
 385         rx_data_read += FIFO_DATA_SIZE;
 386
 387         /* actual count of valid data in word */
 388         *count = ((total_rx_data < rx_data_read) ?
 389                         (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) :
 390                         FIFO_DATA_SIZE);
 391
 392         /* If there are still data left in FIFO we'll read them before
 393          * initializing RX Transfer again
 394          */
 395         if (rx_data_read < total_rx_data)
 396                 return MSM_BOOT_UART_DM_E_SUCCESS;
 397
 398         msm_boot_uart_dm_init_rx_transfer(base);
 399         total_rx_data = rx_data_read = 0;
 400
 401         return MSM_BOOT_UART_DM_E_SUCCESS;
 402 }
 403
 404 void serial_putchar(unsigned data)
 405 {
 406         int num_of_chars = 1;
 407         void *base = uart_board_param.uart_dm_base;
 408
 409         if (data == '\n') {
 410                 num_of_chars++;
 411                 data = (data << 8) | '\r';
 412         }
 413
 414         /* Wait until transmit FIFO is empty. */
 415         while (!(read32(MSM_BOOT_UART_DM_SR(base)) &
 416                  MSM_BOOT_UART_DM_SR_TXEMT))
 417                 udelay(1);
 418         /*
 419          * TX FIFO is ready to accept new character(s). First write number of
 420          * characters to be transmitted.
 421          */
 422         write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars);
 423
 424         /* And now write the character(s) */
 425         write32(MSM_BOOT_UART_DM_TF(base, 0), data);
 426 }
 427
 428 /*
 429  * msm_boot_uart_dm_reset - resets UART controller
 430  * @base: UART controller base address
 431  */
 432 static unsigned int msm_boot_uart_dm_reset(void *base)
 433 {
 434         write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX);
 435         write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX);
 436         write32(MSM_BOOT_UART_DM_CR(base),
 437                 MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT);
 438         write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR);
 439         write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
 440
 441         return MSM_BOOT_UART_DM_E_SUCCESS;
 442 }
 443
 444 /*
 445  * msm_boot_uart_dm_init - Initializes UART controller
 446  * @uart_dm_base: UART controller base address
 447  */
 448 unsigned int msm_boot_uart_dm_init(void  *uart_dm_base)
 449 {
 450         /* Configure UART mode registers MR1 and MR2 */
 451         /* Hardware flow control isn't supported */
 452         write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0);
 453
 454         /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
 455         write32(MSM_BOOT_UART_DM_MR2(uart_dm_base),
 456                 MSM_BOOT_UART_DM_8_N_1_MODE);
 457
 458         /* Configure Interrupt Mask register IMR */
 459         write32(MSM_BOOT_UART_DM_IMR(uart_dm_base),
 460                 MSM_BOOT_UART_DM_IMR_ENABLED);
 461
 462         /*
 463          * Configure Tx and Rx watermarks configuration registers
 464          * TX watermark value is set to 0 - interrupt is generated when
 465          * FIFO level is less than or equal to 0
 466          */
 467         write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base),
 468                 MSM_BOOT_UART_DM_TFW_VALUE);
 469
 470         /* RX watermark value */
 471         write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base),
 472                 MSM_BOOT_UART_DM_RFW_VALUE);
 473
 474         /* Configure Interrupt Programming Register */
 475         /* Set initial Stale timeout value */
 476         write32(MSM_BOOT_UART_DM_IPR(uart_dm_base),
 477                 MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB);
 478
 479         /* Configure IRDA if required */
 480         /* Disabling IRDA mode */
 481         write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0);
 482
 483         /* Configure hunt character value in HCR register */
 484         /* Keep it in reset state */
 485         write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0);
 486
 487         /*
 488          * Configure Rx FIFO base address
 489          * Both TX/RX shares same SRAM and default is half-n-half.
 490          * Sticking with default value now.
 491          * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
 492          * We have found RAM_ADDR_WIDTH = 0x7f
 493          */
 494
 495         /* Issue soft reset command */
 496         msm_boot_uart_dm_reset(uart_dm_base);
 497
 498         /* Enable/Disable Rx/Tx DM interfaces */
 499         /* Data Mover not currently utilized. */
 500         write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0);
 501
 502         /* Enable transmitter */
 503         write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
 504                 MSM_BOOT_UART_DM_CR_TX_ENABLE);
 505
 506         /* Initialize Receive Path */
 507         msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
 508
 509         return 0;
 510 }
 511
 512 /**
 513  * serial_havechar - checks if data available for reading
 514  *
 515  * Returns 1 if data available, 0 otherwise
 516  */
 517 int serial_havechar(void)
 518 {
 519         /* Return if data is already read */
 520         if (valid_data)
 521                 return 1;
 522
 523         /* Read data from the FIFO */
 524         if (msm_boot_uart_dm_read(&word, &valid_data, 0) !=
 525             MSM_BOOT_UART_DM_E_SUCCESS)
 526                 return 0;
 527
 528         return 1;
 529 }
 530
 531 /**
 532  * ipq40xx_serial_getc - reads a character
 533  *
 534  * Returns the character read from serial port.
 535  */
 536 int serial_getchar(void)
 537 {
 538         uint8_t byte;
 539
 540         while (!serial_havechar())
 541                 ;       /* wait for incoming data */
 542
 543         byte = (uint8_t)(word & 0xff);
 544         word = word >> 8;
 545         valid_data--;
 546
 547         return byte;
 548 }
 549
 550 static struct console_input_driver consin = {};
 551 static struct console_output_driver consout = {};
 552
 553 /* For simplicity's sake, let's rely on coreboot initializing the UART. */
 554 void serial_console_init(void)
 555 {
 556         if (!lib_sysinfo.cb_serial)
 557                 return;
 558
 559         consin.havekey = serial_havechar;
 560         consin.getchar = serial_getchar;
 561         consin.input_type = CONSOLE_INPUT_TYPE_UART;
 562
 563         consout.putchar = serial_putchar;
 564
 565         console_add_output_driver(&consout);
 566         console_add_input_driver(&consin);
 567 }