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mb/google/brya/var/uldrenite: Generate RAM ID and SPD file
[coreboot2.git] / payloads / libpayload / drivers / usb / ohci.c
blob79add33fe734eeb961a47b287a7218e854739912
1 /*
2 *
3 * Copyright (C) 2010 Patrick Georgi
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 //#define USB_DEBUG
30
31 #include <arch/virtual.h>
32 #include <inttypes.h>
33 #include <usb/usb.h>
34 #include "ohci_private.h"
35 #include "ohci.h"
36
37 static void ohci_start(hci_t *controller);
38 static void ohci_stop(hci_t *controller);
39 static void ohci_reset(hci_t *controller);
40 static void ohci_shutdown(hci_t *controller);
41 static int ohci_bulk(endpoint_t *ep, int size, u8 *data, int finalize);
42 static int ohci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq,
43 int dalen, u8 *data);
44 static void* ohci_create_intr_queue(endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
45 static void ohci_destroy_intr_queue(endpoint_t *ep, void *queue);
46 static u8* ohci_poll_intr_queue(void *queue);
47 static int ohci_process_done_queue(ohci_t *ohci, int spew_debug);
48
49 #ifdef USB_DEBUG
50 static void
51 dump_td(td_t *cur)
52 {
53 usb_debug("+---------------------------------------------------+\n");
54 if (((cur->config & (3UL << 19)) >> 19) == 0)
55 usb_debug("|..[SETUP]..........................................|\n");
56 else if (((cur->config & (3UL << 8)) >> 8) == 2)
57 usb_debug("|..[IN].............................................|\n");
58 else if (((cur->config & (3UL << 8)) >> 8) == 1)
59 usb_debug("|..[OUT]............................................|\n");
60 else
61 usb_debug("|..[]...............................................|\n");
62 usb_debug("|:|============ OHCI TD at [0x%08lx] ==========|:|\n", virt_to_phys(cur));
63 usb_debug("|:| ERRORS = [%ld] | CONFIG = [0x%08"PRIx32"] | |:|\n",
64 3 - ((cur->config & (3UL << 26)) >> 26), cur->config);
65 usb_debug("|:+-----------------------------------------------+:|\n");
66 usb_debug("|:| C | Condition Code | [%02ld] |:|\n", (cur->config & (0xFUL << 28)) >> 28);
67 usb_debug("|:| O | Direction/PID | [%ld] |:|\n", (cur->config & (3UL << 19)) >> 19);
68 usb_debug("|:| N | Buffer Rounding | [%ld] |:|\n", (cur->config & (1UL << 18)) >> 18);
69 usb_debug("|:| F | Delay Interrupt | [%ld] |:|\n", (cur->config & (7UL << 21)) >> 21);
70 usb_debug("|:| I | Data Toggle | [%ld] |:|\n", (cur->config & (3UL << 24)) >> 24);
71 usb_debug("|:| G | Error Count | [%ld] |:|\n", (cur->config & (3UL << 26)) >> 26);
72 usb_debug("|:+-----------------------------------------------+:|\n");
73 usb_debug("|:| Current Buffer Pointer [0x%08"PRIx32"] |:|\n", cur->current_buffer_pointer);
74 usb_debug("|:+-----------------------------------------------+:|\n");
75 usb_debug("|:| Next TD [0x%08"PRIx32"] |:|\n", cur->next_td);
76 usb_debug("|:+-----------------------------------------------+:|\n");
77 usb_debug("|:| Current Buffer End [0x%08"PRIx32"] |:|\n", cur->buffer_end);
78 usb_debug("|:|-----------------------------------------------|:|\n");
79 usb_debug("|...................................................|\n");
80 usb_debug("+---------------------------------------------------+\n");
81 }
82
83 static void
84 dump_ed(ed_t *cur)
85 {
86 td_t *tmp_td = NULL;
87 usb_debug("+===================================================+\n");
88 usb_debug("| ############# OHCI ED at [0x%08lx] ########### |\n", virt_to_phys(cur));
89 usb_debug("+---------------------------------------------------+\n");
90 usb_debug("| Next Endpoint Descriptor [0x%08lx] |\n", cur->next_ed & ~0xFUL);
91 usb_debug("+---------------------------------------------------+\n");
92 usb_debug("| | @ 0x%08"PRIx32" : |\n", cur->config);
93 usb_debug("| C | Maximum Packet Length | [%04ld] |\n", ((cur->config & (0x3fffUL << 16)) >> 16));
94 usb_debug("| O | Function Address | [%04"PRIx32"] |\n", cur->config & 0x7F);
95 usb_debug("| N | Endpoint Number | [%02ld] |\n", (cur->config & (0xFUL << 7)) >> 7);
96 usb_debug("| F | Endpoint Direction | [%ld] |\n", ((cur->config & (3UL << 11)) >> 11));
97 usb_debug("| I | Endpoint Speed | [%ld] |\n", ((cur->config & (1UL << 13)) >> 13));
98 usb_debug("| G | Skip | [%ld] |\n", ((cur->config & (1UL << 14)) >> 14));
99 usb_debug("| | Format | [%ld] |\n", ((cur->config & (1UL << 15)) >> 15));
100 usb_debug("+---------------------------------------------------+\n");
101 usb_debug("| TD Queue Tail Pointer [0x%08lx] |\n", cur->tail_pointer & ~0xFUL);
102 usb_debug("+---------------------------------------------------+\n");
103 usb_debug("| TD Queue Head Pointer [0x%08lx] |\n", cur->head_pointer & ~0xFUL);
104 usb_debug("| CarryToggleBit [%d] Halted [%d] |\n", (u16)(cur->head_pointer & 0x2UL)>>1, (u16)(cur->head_pointer & 0x1UL));
105
106 tmp_td = (td_t *)phys_to_virt((cur->head_pointer & ~0xFUL));
107 if ((cur->head_pointer & ~0xFUL) != (cur->tail_pointer & ~0xFUL)) {
108 usb_debug("|:::::::::::::::::: OHCI TD CHAIN ::::::::::::::::::|\n");
109 while (virt_to_phys(tmp_td) != (cur->tail_pointer & ~0xFUL))
110 {
111 dump_td(tmp_td);
112 tmp_td = (td_t *)phys_to_virt((tmp_td->next_td & ~0xFUL));
113 }
114 usb_debug("|:::::::::::::::: EOF OHCI TD CHAIN ::::::::::::::::|\n");
115 usb_debug("+---------------------------------------------------+\n");
116 } else {
117 usb_debug("+---------------------------------------------------+\n");
118 }
119 }
120 #endif
121
122 static void
123 ohci_reset(hci_t *controller)
124 {
125 if (controller == NULL)
126 return;
127
128 OHCI_INST(controller)->opreg->HcCommandStatus = HostControllerReset;
129 mdelay(2); /* wait 2ms */
130 OHCI_INST(controller)->opreg->HcControl = 0;
131 mdelay(10); /* wait 10ms */
132 }
133
134 static void
135 ohci_reinit(hci_t *controller)
136 {
137 }
138
139 #if 0 && defined(USB_DEBUG)
140 /* Section 4.3.3 */
141 static const char *completion_codes[] = {
142 "No error",
143 "CRC",
144 "Bit stuffing",
145 "Data toggle mismatch",
146 "Stall",
147 "Device not responding",
148 "PID check failure",
149 "Unexpected PID",
150 "Data overrun",
151 "Data underrun",
152 "--- (10)",
153 "--- (11)",
154 "Buffer overrun",
155 "Buffer underrun",
156 "Not accessed (14)",
157 "Not accessed (15)"
158 };
159
160 /* Section 4.3.1.2 */
161 static const char *direction[] = {
162 "SETUP",
163 "OUT",
164 "IN",
165 "reserved / from TD"
166 };
167 #endif
168
169 hci_t *
170 ohci_init(unsigned long physical_bar)
171 {
172 int i;
173
174 hci_t *controller = new_controller();
175 controller->instance = xzalloc(sizeof(ohci_t));
176 controller->reg_base = (uintptr_t)physical_bar;
177 controller->type = OHCI;
178 controller->start = ohci_start;
179 controller->stop = ohci_stop;
180 controller->reset = ohci_reset;
181 controller->init = ohci_reinit;
182 controller->shutdown = ohci_shutdown;
183 controller->bulk = ohci_bulk;
184 controller->control = ohci_control;
185 controller->set_address = generic_set_address;
186 controller->finish_device_config = NULL;
187 controller->destroy_device = NULL;
188 controller->create_intr_queue = ohci_create_intr_queue;
189 controller->destroy_intr_queue = ohci_destroy_intr_queue;
190 controller->poll_intr_queue = ohci_poll_intr_queue;
191 init_device_entry(controller, 0);
192 OHCI_INST(controller)->roothub = controller->devices[0];
193
194 OHCI_INST(controller)->opreg = (opreg_t*)phys_to_virt(physical_bar);
195 usb_debug("OHCI Version %x.%x\n", (OHCI_INST(controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST(controller)->opreg->HcRevision & 0xf);
196
197 if ((OHCI_INST(controller)->opreg->HcControl & HostControllerFunctionalStateMask) == USBReset) {
198 /* cold boot */
199 OHCI_INST(controller)->opreg->HcControl &= ~RemoteWakeupConnected;
200 OHCI_INST(controller)->opreg->HcFmInterval = (11999 * FrameInterval) | ((((11999 - 210)*6)/7) * FSLargestDataPacket);
201 /* TODO: right value for PowerOnToPowerGoodTime ? */
202 OHCI_INST(controller)->opreg->HcRhDescriptorA = NoPowerSwitching | NoOverCurrentProtection | (10 * PowerOnToPowerGoodTime);
203 OHCI_INST(controller)->opreg->HcRhDescriptorB = (0 * DeviceRemovable);
204 udelay(100); /* TODO: reset asserting according to USB spec */
205 } else if ((OHCI_INST(controller)->opreg->HcControl & HostControllerFunctionalStateMask) != USBOperational) {
206 OHCI_INST(controller)->opreg->HcControl = (OHCI_INST(controller)->opreg->HcControl & ~HostControllerFunctionalStateMask) | USBResume;
207 udelay(100); /* TODO: resume time according to USB spec */
208 }
209 int interval = OHCI_INST(controller)->opreg->HcFmInterval;
210
211 OHCI_INST(controller)->opreg->HcCommandStatus = HostControllerReset;
212 udelay(10); /* at most 10us for reset to complete. State must be set to Operational within 2ms (5.1.1.4) */
213 OHCI_INST(controller)->opreg->HcFmInterval = interval;
214 OHCI_INST(controller)->hcca = dma_memalign(256, 256);
215 if (!OHCI_INST(controller)->hcca)
216 fatal("Not enough DMA memory for OHCI HCCA.\n");
217 memset((void*)OHCI_INST(controller)->hcca, 0, 256);
218
219 if (dma_initialized()) {
220 OHCI_INST(controller)->dma_buffer = dma_memalign(4096, DMA_SIZE);
221 if (!OHCI_INST(controller)->dma_buffer)
222 fatal("Not enough DMA memory for OHCI bounce buffer.\n");
223 }
224
225 /* Initialize interrupt table. */
226 u32 *const intr_table = OHCI_INST(controller)->hcca->HccaInterruptTable;
227 ed_t *const periodic_ed = dma_memalign(sizeof(ed_t), sizeof(ed_t));
228 if (!periodic_ed)
229 fatal("Not enough DMA memory for OHCI interrupt table.\n");
230 memset((void *)periodic_ed, 0, sizeof(*periodic_ed));
231 for (i = 0; i < 32; ++i)
232 intr_table[i] = virt_to_phys(periodic_ed);
233 OHCI_INST(controller)->periodic_ed = periodic_ed;
234
235 OHCI_INST(controller)->opreg->HcHCCA = virt_to_phys(OHCI_INST(controller)->hcca);
236 /* Make sure periodic schedule is enabled. */
237 OHCI_INST(controller)->opreg->HcControl |= PeriodicListEnable;
238 OHCI_INST(controller)->opreg->HcControl &= ~IsochronousEnable; // unused by this driver
239 // disable everything, contrary to what OHCI spec says in 5.1.1.4, as we don't need IRQs
240 OHCI_INST(controller)->opreg->HcInterruptEnable = 1 << 31;
241 OHCI_INST(controller)->opreg->HcInterruptDisable = ~(1 << 31);
242 OHCI_INST(controller)->opreg->HcInterruptStatus = ~0;
243 OHCI_INST(controller)->opreg->HcPeriodicStart = (((OHCI_INST(controller)->opreg->HcFmInterval & FrameIntervalMask) / 10) * 9);
244 OHCI_INST(controller)->opreg->HcControl = (OHCI_INST(controller)->opreg->HcControl & ~HostControllerFunctionalStateMask) | USBOperational;
245
246 mdelay(100);
247
248 controller->devices[0]->controller = controller;
249 controller->devices[0]->init = ohci_rh_init;
250 controller->devices[0]->init(controller->devices[0]);
251 return controller;
252 }
253
254 #if CONFIG(LP_USB_PCI)
255 hci_t *
256 ohci_pci_init(pcidev_t addr)
257 {
258 u32 reg_base;
259
260 /* regarding OHCI spec, Appendix A, BAR_OHCI register description, Table A-4
261 * BASE ADDRESS only [31-12] bits. All other usually 0, but not all.
262 * OHCI mandates MMIO, so bit 0 is clear */
263 reg_base = pci_read_config32(addr, 0x10) & 0xfffff000;
264
265 return ohci_init((unsigned long)reg_base);
266 }
267 #endif
268
269 static void
270 ohci_shutdown(hci_t *controller)
271 {
272 if (controller == 0)
273 return;
274 detach_controller(controller);
275 ohci_stop(controller);
276 ohci_reset(controller);
277 free(OHCI_INST(controller)->hcca);
278 free((void *)OHCI_INST(controller)->periodic_ed);
279 free(OHCI_INST(controller));
280 free(controller);
281 }
282
283 static void
284 ohci_start(hci_t *controller)
285 {
286 OHCI_INST(controller)->opreg->HcControl |= PeriodicListEnable;
287 }
288
289 static void
290 ohci_stop(hci_t *controller)
291 {
292 OHCI_INST(controller)->opreg->HcControl &= ~PeriodicListEnable;
293 }
294
295 #define OHCI_SLEEP_TIME_US 1000
296
297 static int
298 wait_for_ed(usbdev_t *dev, ed_t *head, int pages)
299 {
300 /* wait for results */
301 int timeout = USB_MAX_PROCESSING_TIME_US / OHCI_SLEEP_TIME_US;
302 while (((head->head_pointer & ~3) != head->tail_pointer) &&
303 !(head->head_pointer & 1) &&
304 ((((td_t*)phys_to_virt(head->head_pointer & ~3))->config
305 & TD_CC_MASK) >= TD_CC_NOACCESS) &&
306 timeout--) {
307 /* don't log every ms */
308 if (!(timeout % 100))
309 usb_debug("intst: %x; ctrl: %x; cmdst: %x; head: %x -> %x, tail: %x, condition: %x\n",
310 OHCI_INST(dev->controller)->opreg->HcInterruptStatus,
311 OHCI_INST(dev->controller)->opreg->HcControl,
312 OHCI_INST(dev->controller)->opreg->HcCommandStatus,
313 head->head_pointer,
314 ((td_t*)phys_to_virt(head->head_pointer & ~3))->next_td,
315 head->tail_pointer,
316 (((td_t*)phys_to_virt(head->head_pointer & ~3))->config & TD_CC_MASK) >> TD_CC_SHIFT);
317 udelay(OHCI_SLEEP_TIME_US);
318 }
319 if (timeout <= 0)
320 usb_debug("Error: ohci: endpoint "
321 "descriptor processing timed out.\n");
322 /* Clear the done queue. */
323 int result = ohci_process_done_queue(OHCI_INST(dev->controller), 1);
324
325 if (head->head_pointer & 1) {
326 usb_debug("HALTED!\n");
327 return -1;
328 }
329 return result;
330 }
331
332 static void
333 ohci_free_ed(ed_t *const head)
334 {
335 /* In case the transfer canceled, we have to free unprocessed TDs. */
336 while ((head->head_pointer & ~0x3) != head->tail_pointer) {
337 /* Save current TD pointer. */
338 td_t *const cur_td =
339 (td_t*)phys_to_virt(head->head_pointer & ~0x3);
340 /* Advance head pointer. */
341 head->head_pointer = cur_td->next_td;
342 /* Free current TD. */
343 free((void *)cur_td);
344 }
345
346 /* Always free the dummy TD */
347 if ((head->head_pointer & ~0x3) == head->tail_pointer)
348 free(phys_to_virt(head->head_pointer & ~0x3));
349 /* and the ED. */
350 free((void *)head);
351 }
352
353 static int
354 ohci_control(usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,
355 unsigned char *src)
356 {
357 u8 *data = src;
358 u8 *devreq = setup;
359 int remaining = dalen;
360 td_t *cur;
361
362 if (!dma_coherent(devreq)) {
363 devreq = OHCI_INST(dev->controller)->dma_buffer;
364 memcpy(devreq, setup, drlen);
365 }
366 if (dalen > 0 && !dma_coherent(src)) {
367 data = OHCI_INST(dev->controller)->dma_buffer + drlen;
368 if (drlen + dalen > DMA_SIZE) {
369 usb_debug("OHCI control transfer too large for DMA buffer: %d\n", drlen + dalen);
370 return -1;
371 }
372 if (dir == OUT)
373 memcpy(data, src, dalen);
374 }
375
376 // pages are specified as 4K in OHCI, so don't use getpagesize()
377 int first_page = (unsigned long)data / 4096;
378 int last_page = (unsigned long)(data+dalen-1)/4096;
379 if (last_page < first_page) last_page = first_page;
380 int pages = (dalen == 0)?0:(last_page - first_page + 1);
381
382 /* First TD. */
383 td_t *const first_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
384 if (!first_td)
385 fatal("Not enough DMA memory for OHCI first TD in buffer.\n");
386 memset((void *)first_td, 0, sizeof(*first_td));
387 cur = first_td;
388
389 cur->config = TD_DIRECTION_SETUP |
390 TD_DELAY_INTERRUPT_NOINTR |
391 TD_TOGGLE_FROM_TD |
392 TD_TOGGLE_DATA0 |
393 TD_CC_NOACCESS;
394 cur->current_buffer_pointer = virt_to_phys(devreq);
395 cur->buffer_end = virt_to_phys(devreq + drlen - 1);
396
397 while (pages > 0) {
398 /* One more TD. */
399 td_t *const next = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
400 if (!next)
401 fatal("Not enough DMA memory for OHCI new page.\n");
402 memset((void *)next, 0, sizeof(*next));
403 /* Linked to the previous. */
404 cur->next_td = virt_to_phys(next);
405 /* Advance to the new TD. */
406 cur = next;
407
408 cur->config = (dir == IN ? TD_DIRECTION_IN : TD_DIRECTION_OUT) |
409 TD_DELAY_INTERRUPT_NOINTR |
410 TD_TOGGLE_FROM_ED |
411 TD_CC_NOACCESS;
412 cur->current_buffer_pointer = virt_to_phys(data);
413 pages--;
414 int consumed = (4096 - ((unsigned long)data % 4096));
415 if (consumed >= remaining) {
416 // end of data is within same page
417 cur->buffer_end = virt_to_phys(data + remaining - 1);
418 remaining = 0;
419 /* assert(pages == 0); */
420 } else {
421 remaining -= consumed;
422 data += consumed;
423 pages--;
424 int second_page_size = remaining;
425 if (remaining > 4096) {
426 second_page_size = 4096;
427 }
428 cur->buffer_end = virt_to_phys(data + second_page_size - 1);
429 remaining -= second_page_size;
430 data += second_page_size;
431 }
432 }
433
434 /* One more TD. */
435 td_t *const next_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
436 if (!next_td)
437 fatal("Not enough DMA memory for OHCI additional TD.\n");
438 memset((void *)next_td, 0, sizeof(*next_td));
439 /* Linked to the previous. */
440 cur->next_td = virt_to_phys(next_td);
441 /* Advance to the new TD. */
442 cur = next_td;
443 cur->config = (dir == IN ? TD_DIRECTION_OUT : TD_DIRECTION_IN) |
444 TD_DELAY_INTERRUPT_ZERO | /* Write done head after this TD. */
445 TD_TOGGLE_FROM_TD |
446 TD_TOGGLE_DATA1 |
447 TD_CC_NOACCESS;
448 cur->current_buffer_pointer = 0;
449 cur->buffer_end = 0;
450
451 /* Final dummy TD. */
452 td_t *const final_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
453 if (!final_td)
454 fatal("Not enough DMA memory for OHCI dummy TD!\n");
455 memset((void *)final_td, 0, sizeof(*final_td));
456 /* Linked to the previous. */
457 cur->next_td = virt_to_phys(final_td);
458
459 /* Data structures */
460 ed_t *head = dma_memalign(sizeof(ed_t), sizeof(ed_t));
461 if (!head)
462 fatal("Not enough DMA memory for OHCI data structures.\n");
463 memset((void*)head, 0, sizeof(*head));
464 head->config = (dev->address << ED_FUNC_SHIFT) |
465 (0 << ED_EP_SHIFT) |
466 (OHCI_FROM_TD << ED_DIR_SHIFT) |
467 (dev->speed?ED_LOWSPEED:0) |
468 (dev->endpoints[0].maxpacketsize << ED_MPS_SHIFT);
469 head->tail_pointer = virt_to_phys(final_td);
470 head->head_pointer = virt_to_phys(first_td);
471
472 usb_debug("%s(): doing transfer with %x. first_td at %"PRIxPTR"\n", __func__,
473 head->config & ED_FUNC_MASK, virt_to_phys(first_td));
474 #ifdef USB_DEBUG
475 dump_ed(head);
476 #endif
477
478 /* activate schedule */
479 OHCI_INST(dev->controller)->opreg->HcControlHeadED = virt_to_phys(head);
480 OHCI_INST(dev->controller)->opreg->HcControl |= ControlListEnable;
481 OHCI_INST(dev->controller)->opreg->HcCommandStatus = ControlListFilled;
482
483 int result = wait_for_ed(dev, head,
484 (dalen == 0)?0:(last_page - first_page + 1));
485 /* Wait some frames before and one after disabling list access. */
486 mdelay(4);
487 OHCI_INST(dev->controller)->opreg->HcControl &= ~ControlListEnable;
488 mdelay(1);
489
490 /* free memory */
491 ohci_free_ed(head);
492
493 if (result >= 0) {
494 result = dalen - result;
495 if (dir == IN && data != src)
496 memcpy(src, data, result);
497 }
498
499 return result;
500 }
501
502 /* finalize == 1: if data is of packet aligned size, add a zero length packet */
503 static int
504 ohci_bulk(endpoint_t *ep, int dalen, u8 *src, int finalize)
505 {
506 int i;
507 td_t *cur, *next;
508 int remaining = dalen;
509 u8 *data = src;
510 usb_debug("bulk: %x bytes from %p, finalize: %x, maxpacketsize: %x\n", dalen, src, finalize, ep->maxpacketsize);
511
512 if (!dma_coherent(src)) {
513 data = OHCI_INST(ep->dev->controller)->dma_buffer;
514 if (dalen > DMA_SIZE) {
515 usb_debug("OHCI bulk transfer too large for DMA buffer: %d\n", dalen);
516 return -1;
517 }
518 if (ep->direction == OUT)
519 memcpy(data, src, dalen);
520 }
521
522 // pages are specified as 4K in OHCI, so don't use getpagesize()
523 int first_page = (unsigned long)data / 4096;
524 int last_page = (unsigned long)(data+dalen-1)/4096;
525 if (last_page < first_page) last_page = first_page;
526 int pages = (dalen == 0)?0:(last_page - first_page + 1);
527 int td_count = (pages+1)/2;
528
529 if (finalize && ((dalen % ep->maxpacketsize) == 0)) {
530 td_count++;
531 }
532
533 /* First TD. */
534 td_t *const first_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
535 if (!first_td)
536 fatal("Not enough DMA memory for OHCI bulk transfer.\n");
537 memset((void *)first_td, 0, sizeof(*first_td));
538 cur = next = first_td;
539
540 for (i = 0; i < td_count; ++i) {
541 /* Advance to next TD. */
542 cur = next;
543 cur->config = (ep->direction == IN ? TD_DIRECTION_IN : TD_DIRECTION_OUT) |
544 TD_DELAY_INTERRUPT_NOINTR |
545 TD_TOGGLE_FROM_ED |
546 TD_CC_NOACCESS;
547 cur->current_buffer_pointer = virt_to_phys(data);
548 pages--;
549 if (remaining == 0) {
550 /* magic TD for empty packet transfer */
551 cur->current_buffer_pointer = 0;
552 cur->buffer_end = 0;
553 /* assert((pages == 0) && finalize); */
554 }
555 int consumed = (4096 - ((unsigned long)data % 4096));
556 if (consumed >= remaining) {
557 // end of data is within same page
558 cur->buffer_end = virt_to_phys(data + remaining - 1);
559 remaining = 0;
560 /* assert(pages == finalize); */
561 } else {
562 remaining -= consumed;
563 data += consumed;
564 pages--;
565 int second_page_size = remaining;
566 if (remaining > 4096) {
567 second_page_size = 4096;
568 }
569 cur->buffer_end = virt_to_phys(data + second_page_size - 1);
570 remaining -= second_page_size;
571 data += second_page_size;
572 }
573 /* One more TD. */
574 next = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
575 if (!next)
576 fatal("Not enough DMA mem for TD bulk transfer.\n");
577 memset((void *)next, 0, sizeof(*next));
578 /* Linked to the previous. */
579 cur->next_td = virt_to_phys(next);
580 }
581
582 /* Write done head after last TD. */
583 cur->config &= ~TD_DELAY_INTERRUPT_MASK;
584 /* Advance to final, dummy TD. */
585 cur = next;
586
587 /* Data structures */
588 ed_t *head = dma_memalign(sizeof(ed_t), sizeof(ed_t));
589 if (!head)
590 fatal("Not enough DMA memory for OHCI bulk transfer's head.\n");
591 memset((void*)head, 0, sizeof(*head));
592 head->config = (ep->dev->address << ED_FUNC_SHIFT) |
593 ((ep->endpoint & 0xf) << ED_EP_SHIFT) |
594 (((ep->direction == IN)?OHCI_IN:OHCI_OUT) << ED_DIR_SHIFT) |
595 (ep->dev->speed?ED_LOWSPEED:0) |
596 (ep->maxpacketsize << ED_MPS_SHIFT);
597 head->tail_pointer = virt_to_phys(cur);
598 head->head_pointer = virt_to_phys(first_td) | (ep->toggle?ED_TOGGLE:0);
599
600 usb_debug("doing bulk transfer with %x(%x). first_td at %"PRIxPTR", last %"PRIxPTR"\n",
601 head->config & ED_FUNC_MASK,
602 (head->config & ED_EP_MASK) >> ED_EP_SHIFT,
603 virt_to_phys(first_td), virt_to_phys(cur));
604
605 /* activate schedule */
606 OHCI_INST(ep->dev->controller)->opreg->HcBulkHeadED = virt_to_phys(head);
607 OHCI_INST(ep->dev->controller)->opreg->HcControl |= BulkListEnable;
608 OHCI_INST(ep->dev->controller)->opreg->HcCommandStatus = BulkListFilled;
609
610 int result = wait_for_ed(ep->dev, head,
611 (dalen == 0)?0:(last_page - first_page + 1));
612 /* Wait some frames before and one after disabling list access. */
613 mdelay(4);
614 OHCI_INST(ep->dev->controller)->opreg->HcControl &= ~BulkListEnable;
615 mdelay(1);
616
617 ep->toggle = head->head_pointer & ED_TOGGLE;
618
619 /* free memory */
620 ohci_free_ed(head);
621
622 if (result >= 0) {
623 result = dalen - result;
624 if (ep->direction == IN && data != src)
625 memcpy(src, data, result);
626 }
627
628 return result;
629 }
630
631 struct _intr_queue;
632
633 struct _intrq_td {
634 volatile td_t td;
635 u8 *data;
636 struct _intrq_td *next;
637 struct _intr_queue *intrq;
638 };
639
640 struct _intr_queue {
641 volatile ed_t ed;
642 struct _intrq_td *head;
643 struct _intrq_td *tail;
644 u8 *data;
645 int reqsize;
646 endpoint_t *endp;
647 unsigned int remaining_tds;
648 int destroy;
649 };
650
651 typedef struct _intrq_td intrq_td_t;
652 typedef struct _intr_queue intr_queue_t;
653
654 #define INTRQ_TD_FROM_TD(x) ((intrq_td_t *)x)
655
656 static void
657 ohci_fill_intrq_td(intrq_td_t *const td, intr_queue_t *const intrq,
658 u8 *const data)
659 {
660 memset(td, 0, sizeof(*td));
661 td->td.config = TD_QUEUETYPE_INTR |
662 (intrq->endp->direction == IN
663 ? TD_DIRECTION_IN : TD_DIRECTION_OUT) |
664 TD_DELAY_INTERRUPT_ZERO |
665 TD_TOGGLE_FROM_ED |
666 TD_CC_NOACCESS;
667 td->td.current_buffer_pointer = virt_to_phys(data);
668 td->td.buffer_end = td->td.current_buffer_pointer + intrq->reqsize - 1;
669 td->intrq = intrq;
670 td->data = data;
671 }
672
673 /* create and hook-up an intr queue into device schedule */
674 static void *
675 ohci_create_intr_queue(endpoint_t *const ep, const int reqsize,
676 const int reqcount, const int reqtiming)
677 {
678 int i;
679 intrq_td_t *first_td = NULL, *last_td = NULL;
680
681 if (reqsize > 4096)
682 return NULL;
683
684 intr_queue_t *const intrq =
685 (intr_queue_t *)dma_memalign(sizeof(intrq->ed), sizeof(*intrq));
686 if (!intrq) {
687 usb_debug("Not enough DMA memory for intr queue.\n");
688 free(intrq);
689 return NULL;
690 }
691 memset(intrq, 0, sizeof(*intrq));
692 intrq->data = (u8 *)dma_malloc(reqcount * reqsize);
693 intrq->reqsize = reqsize;
694 intrq->endp = ep;
695
696 /* Create #reqcount TDs. */
697 u8 *cur_data = intrq->data;
698 for (i = 0; i < reqcount; ++i) {
699 intrq_td_t *const td = dma_memalign(sizeof(td->td), sizeof(*td));
700 if (!td)
701 fatal("Not enough DMA mem to transfer descriptor.\n");
702 ++intrq->remaining_tds;
703 ohci_fill_intrq_td(td, intrq, cur_data);
704 cur_data += reqsize;
705 if (!first_td)
706 first_td = td;
707 else
708 last_td->td.next_td = virt_to_phys(&td->td);
709 last_td = td;
710 }
711
712 /* Create last, dummy TD. */
713 intrq_td_t *dummy_td = dma_memalign(sizeof(dummy_td->td), sizeof(*dummy_td));
714 if (!dummy_td)
715 fatal("Not enough memory to add dummy TD.\n");
716 memset(dummy_td, 0, sizeof(*dummy_td));
717 dummy_td->intrq = intrq;
718 if (last_td)
719 last_td->td.next_td = virt_to_phys(&dummy_td->td);
720 last_td = dummy_td;
721
722 /* Initialize ED. */
723 intrq->ed.config = (ep->dev->address << ED_FUNC_SHIFT) |
724 ((ep->endpoint & 0xf) << ED_EP_SHIFT) |
725 (((ep->direction == IN) ? OHCI_IN : OHCI_OUT) << ED_DIR_SHIFT) |
726 (ep->dev->speed ? ED_LOWSPEED : 0) |
727 (ep->maxpacketsize << ED_MPS_SHIFT);
728 intrq->ed.tail_pointer = virt_to_phys(last_td);
729 intrq->ed.head_pointer = virt_to_phys(first_td) |
730 (ep->toggle ? ED_TOGGLE : 0);
731
732 /* Insert ED into periodic table. */
733 int nothing_placed = 1;
734 ohci_t *const ohci = OHCI_INST(ep->dev->controller);
735 u32 *const intr_table = ohci->hcca->HccaInterruptTable;
736 const u32 dummy_ptr = virt_to_phys(ohci->periodic_ed);
737 for (i = 0; i < 32; i += reqtiming) {
738 /* Advance to the next free position. */
739 while ((i < 32) && (intr_table[i] != dummy_ptr)) ++i;
740 if (i < 32) {
741 intr_table[i] = virt_to_phys(&intrq->ed);
742 nothing_placed = 0;
743 }
744 }
745 if (nothing_placed) {
746 usb_debug("Error: Failed to place ohci interrupt endpoint "
747 "descriptor into periodic table: no space left\n");
748 ohci_destroy_intr_queue(ep, intrq);
749 return NULL;
750 }
751
752 return intrq;
753 }
754
755 /* remove queue from device schedule, dropping all data that came in */
756 static void
757 ohci_destroy_intr_queue(endpoint_t *const ep, void *const q_)
758 {
759 intr_queue_t *const intrq = (intr_queue_t *)q_;
760
761 int i;
762
763 /* Remove interrupt queue from periodic table. */
764 ohci_t *const ohci = OHCI_INST(ep->dev->controller);
765 u32 *const intr_table = ohci->hcca->HccaInterruptTable;
766 for (i = 0; i < 32; ++i) {
767 if (intr_table[i] == virt_to_phys(intrq))
768 intr_table[i] = virt_to_phys(ohci->periodic_ed);
769 }
770 /* Wait for frame to finish. */
771 mdelay(1);
772
773 /* Free unprocessed TDs. */
774 while ((intrq->ed.head_pointer & ~0x3) != intrq->ed.tail_pointer) {
775 td_t *const cur_td =
776 (td_t *)phys_to_virt(intrq->ed.head_pointer & ~0x3);
777 intrq->ed.head_pointer = cur_td->next_td;
778 free(INTRQ_TD_FROM_TD(cur_td));
779 --intrq->remaining_tds;
780 }
781 /* Free final, dummy TD. */
782 free(phys_to_virt(intrq->ed.head_pointer & ~0x3));
783 /* Free data buffer. */
784 free(intrq->data);
785
786 /* Free TDs already fetched from the done queue. */
787 ohci_process_done_queue(ohci, 1);
788 while (intrq->head) {
789 intrq_td_t *const cur_td = intrq->head;
790 intrq->head = intrq->head->next;
791 free(cur_td);
792 --intrq->remaining_tds;
793 }
794
795 /* Mark interrupt queue to be destroyed.
796 ohci_process_done_queue() will free the remaining TDs
797 and finish the interrupt queue off once all TDs are gone. */
798 intrq->destroy = 1;
799
800 /* Save data toggle. */
801 ep->toggle = intrq->ed.head_pointer & ED_TOGGLE;
802 }
803
804 /* read one intr-packet from queue, if available. extend the queue for new input.
805 return NULL if nothing new available.
806 Recommended use: while (data=poll_intr_queue(q)) process(data);
807 */
808 static u8 *
809 ohci_poll_intr_queue(void *const q_)
810 {
811 intr_queue_t *const intrq = (intr_queue_t *)q_;
812
813 u8 *data = NULL;
814
815 /* Process done queue first, then check if we have work to do. */
816 ohci_process_done_queue(OHCI_INST(intrq->endp->dev->controller), 0);
817
818 if (intrq->head) {
819 /* Save pointer to processed TD and advance. */
820 intrq_td_t *const cur_td = intrq->head;
821 intrq->head = cur_td->next;
822
823 /* Return data buffer of this TD. */
824 data = cur_td->data;
825
826 /* Requeue this TD (i.e. copy to dummy and requeue as dummy). */
827 intrq_td_t *const dummy_td =
828 INTRQ_TD_FROM_TD(phys_to_virt(intrq->ed.tail_pointer));
829 ohci_fill_intrq_td(dummy_td, intrq, cur_td->data);
830 /* Reset all but intrq pointer (i.e. init as dummy). */
831 memset(cur_td, 0, sizeof(*cur_td));
832 cur_td->intrq = intrq;
833 /* Insert into interrupt queue as dummy. */
834 dummy_td->td.next_td = virt_to_phys(&cur_td->td);
835 intrq->ed.tail_pointer = virt_to_phys(&cur_td->td);
836 }
837
838 return data;
839 }
840
841 static int
842 ohci_process_done_queue(ohci_t *const ohci, const int spew_debug)
843 {
844 /* returns the amount of bytes *not* transmitted for short packets */
845 int result = 0;
846 int i, j;
847
848 /* Temporary queue of interrupt queue TDs (to reverse order). */
849 intrq_td_t *temp_tdq = NULL;
850
851 /* Check if done head has been written. */
852 if (!(ohci->opreg->HcInterruptStatus & WritebackDoneHead))
853 return 0;
854 /* Fetch current done head.
855 Lsb is only interesting for hw interrupts. */
856 u32 phys_done_queue = ohci->hcca->HccaDoneHead & ~1;
857 /* Tell host controller, he may overwrite the done head pointer. */
858 ohci->opreg->HcInterruptStatus = WritebackDoneHead;
859
860 i = 0;
861 /* Process done queue (it's in reversed order). */
862 while (phys_done_queue) {
863 td_t *const done_td = (td_t *)phys_to_virt(phys_done_queue);
864
865 /* Advance pointer to next TD. */
866 phys_done_queue = done_td->next_td;
867
868 switch (done_td->config & TD_QUEUETYPE_MASK) {
869 case TD_QUEUETYPE_ASYNC:
870 /* Free processed async TDs and count short transfer. */
871 if (done_td->current_buffer_pointer)
872 result += (done_td->buffer_end & 0xfff) -
873 (done_td->current_buffer_pointer
874 & 0xfff) + 1;
875 free((void *)done_td);
876 break;
877 case TD_QUEUETYPE_INTR: {
878 intrq_td_t *const td = INTRQ_TD_FROM_TD(done_td);
879 intr_queue_t *const intrq = td->intrq;
880 /* Check if the corresponding interrupt
881 queue is still being processed. */
882 if (intrq->destroy) {
883 /* Free this TD, and */
884 free(td);
885 --intrq->remaining_tds;
886 usb_debug("Freed TD from orphaned interrupt "
887 "queue, %d TDs remain.\n",
888 intrq->remaining_tds);
889 /* the interrupt queue if it has no more TDs. */
890 if (!intrq->remaining_tds)
891 free(intrq);
892 } else {
893 /* Save done TD to be processed. */
894 td->next = temp_tdq;
895 temp_tdq = td;
896 }
897 break;
898 }
899 default:
900 break;
901 }
902 ++i;
903 }
904 if (spew_debug)
905 usb_debug("Processed %d done TDs.\n", i);
906
907 j = 0;
908 /* Process interrupt queue TDs in right order. */
909 while (temp_tdq) {
910 /* Save pointer of current TD and advance. */
911 intrq_td_t *const cur_td = temp_tdq;
912 temp_tdq = temp_tdq->next;
913
914 /* The interrupt queue for the current TD. */
915 intr_queue_t *const intrq = cur_td->intrq;
916 /* Append to interrupt queue. */
917 if (!intrq->head) {
918 /* First element. */
919 intrq->head = intrq->tail = cur_td;
920 } else {
921 /* Insert at tail. */
922 intrq->tail->next = cur_td;
923 intrq->tail = cur_td;
924 }
925 /* It's always the last element. */
926 cur_td->next = NULL;
927 ++j;
928 }
929 if (spew_debug)
930 usb_debug("processed %d done tds, %d intr tds thereof.\n", i, j);
931
932 return result;
933 }
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