src/arch/x86/cf9_reset.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/io.h>
   4 #include <arch/cache.h>
   5 #include <cf9_reset.h>
   6 #include <console/console.h>
   7 #include <halt.h>
   8
   9 /*
  10  * A system reset in terms of the CF9 register asserts the INIT#
  11  * signal to reset the CPU along the PLTRST# signal to reset other
  12  * board components. It is usually the hardest reset type that
  13  * does not power cycle the board. Thus, it could be called a
  14  * "warm reset".
  15  */
  16 void do_system_reset(void)
  17 {
  18         dcache_clean_all();
  19         outb(SYS_RST, RST_CNT);
  20         outb(RST_CPU | SYS_RST, RST_CNT);
  21 }
  22
  23 /*
  24  * A full reset in terms of the CF9 register triggers a power cycle
  25  * (i.e. S0 -> S5 -> S0 transition). Thus, it could be called a
  26  * "cold reset".
  27  * Note: Not all x86 implementations comply with this definition,
  28  *       some may require additional configuration to power cycle.
  29  */
  30 void do_full_reset(void)
  31 {
  32         dcache_clean_all();
  33         outb(FULL_RST | SYS_RST, RST_CNT);
  34         outb(FULL_RST | RST_CPU | SYS_RST, RST_CNT);
  35 }
  36
  37 void system_reset(void)
  38 {
  39         printk(BIOS_INFO, "%s() called!\n", __func__);
  40         cf9_reset_prepare();
  41         do_system_reset();
  42         halt();
  43 }
  44
  45 void full_reset(void)
  46 {
  47         printk(BIOS_INFO, "%s() called!\n", __func__);
  48         cf9_reset_prepare();
  49         do_full_reset();
  50         halt();
  51 }