src/arch/x86/ioapic.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <device/device.h>
   5 #include <device/mmio.h>
   6 #include <arch/ioapic.h>
   7 #include <console/console.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <inttypes.h>
  10 #include <types.h>
  11
  12 #define ALL             (0xff << 24)
  13 #define NONE            (0)
  14 #define INT_DISABLED    (1 << 16)
  15 #define INT_ENABLED     (0 << 16)
  16 #define TRIGGER_EDGE    (0 << 15)
  17 #define TRIGGER_LEVEL   (1 << 15)
  18 #define POLARITY_HIGH   (0 << 13)
  19 #define POLARITY_LOW    (1 << 13)
  20 #define PHYSICAL_DEST   (0 << 11)
  21 #define LOGICAL_DEST    (1 << 11)
  22 #define ExtINT          (7 << 8)
  23 #define NMI             (4 << 8)
  24 #define SMI             (2 << 8)
  25 #define INT             (1 << 8)
  26
  27 static u32 io_apic_read(uintptr_t ioapic_base, u32 reg)
  28 {
  29         write32p(ioapic_base, reg);
  30         return read32p(ioapic_base + 0x10);
  31 }
  32
  33 static void io_apic_write(uintptr_t ioapic_base, u32 reg, u32 value)
  34 {
  35         write32p(ioapic_base, reg);
  36         write32p(ioapic_base + 0x10, value);
  37 }
  38
  39 static void write_vector(uintptr_t ioapic_base, u8 vector, u32 high, u32 low)
  40 {
  41         io_apic_write(ioapic_base, vector * 2 + 0x10, low);
  42         io_apic_write(ioapic_base, vector * 2 + 0x11, high);
  43
  44         printk(BIOS_SPEW, "IOAPIC: vector 0x%02x value 0x%08x 0x%08x\n",
  45                vector, high, low);
  46 }
  47
  48 /* Bits 23-16 of register 0x01 specify the maximum redirection entry, which
  49  * is the number of interrupts minus 1. */
  50 unsigned int ioapic_get_max_vectors(uintptr_t ioapic_base)
  51 {
  52         u32 reg;
  53         u8 count;
  54
  55         reg = io_apic_read(ioapic_base, 0x01);
  56         count = (reg >> 16) & 0xff;
  57
  58         if (count == 0xff)
  59                 count = 23;
  60         count++;
  61
  62         printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", count);
  63         return count;
  64 }
  65
  66 /* Set maximum number of redirection entries (MRE). It is write-once register
  67  * for some chipsets, and a negative mre_count will lock it to the number
  68  * of vectors read from the register. */
  69 void ioapic_set_max_vectors(uintptr_t ioapic_base, int mre_count)
  70 {
  71         u32 reg;
  72         u8 count;
  73
  74         reg = io_apic_read(ioapic_base, 0x01);
  75         count = (reg >> 16) & 0xff;
  76         if (mre_count > 0)
  77                 count = mre_count - 1;
  78         reg &= ~(0xff << 16);
  79         reg |= count << 16;
  80         io_apic_write(ioapic_base, 0x01, reg);
  81 }
  82
  83 void ioapic_lock_max_vectors(uintptr_t ioapic_base)
  84 {
  85         ioapic_set_max_vectors(ioapic_base, -1);
  86 }
  87
  88 static void clear_vectors(uintptr_t ioapic_base, u8 first, u8 last)
  89 {
  90         u32 low, high;
  91         u8 i;
  92
  93         printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %" PRIxPTR "\n", ioapic_base);
  94
  95         low = INT_DISABLED;
  96         high = NONE;
  97
  98         for (i = first; i <= last; i++)
  99                 write_vector(ioapic_base, i, high, low);
 100
 101         if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
 102                 printk(BIOS_WARNING, "IOAPIC not responding.\n");
 103                 return;
 104         }
 105 }
 106
 107 static void route_i8259_irq0(uintptr_t ioapic_base)
 108 {
 109         u32 bsp_lapicid = lapicid();
 110         u32 low, high;
 111
 112         ASSERT(bsp_lapicid < 255);
 113
 114         printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
 115                bsp_lapicid);
 116
 117         /* Enable Virtual Wire Mode. Should this be LOGICAL_DEST instead? */
 118         low = INT_ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
 119         high = bsp_lapicid << (56 - 32);
 120
 121         write_vector(ioapic_base, 0, high, low);
 122
 123         if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
 124                 printk(BIOS_WARNING, "IOAPIC not responding.\n");
 125                 return;
 126         }
 127 }
 128
 129 static void set_ioapic_id(uintptr_t ioapic_base, u8 ioapic_id)
 130 {
 131         int i;
 132
 133         printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %" PRIxPTR "\n",
 134                ioapic_base);
 135         printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
 136
 137         io_apic_write(ioapic_base, 0x00,
 138                       (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | (ioapic_id << 24));
 139
 140         printk(BIOS_SPEW, "IOAPIC: Dumping registers\n");
 141         for (i = 0; i < 3; i++)
 142                 printk(BIOS_SPEW, "  reg 0x%04x: 0x%08x\n", i,
 143                        io_apic_read(ioapic_base, i));
 144 }
 145
 146 u8 get_ioapic_id(uintptr_t ioapic_base)
 147 {
 148         /*
 149          * According to 82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)
 150          * only 4 bits (24:27) are used for the ID. In practice the upper bits are either
 151          * always 0 or used for larger IDs.
 152          */
 153         return (io_apic_read(ioapic_base, 0x00) >> 24) & 0xff;
 154 }
 155
 156 u8 get_ioapic_version(uintptr_t ioapic_base)
 157 {
 158         return io_apic_read(ioapic_base, 0x01) & 0xff;
 159 }
 160
 161 void ioapic_set_boot_config(uintptr_t ioapic_base, bool irq_on_fsb)
 162 {
 163         if (irq_on_fsb) {
 164                 /*
 165                  * For the Pentium 4 and above APICs deliver their interrupts
 166                  * on the front side bus, enable that.
 167                  */
 168                 printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
 169                 io_apic_write(ioapic_base, 0x03,
 170                               io_apic_read(ioapic_base, 0x03) | (1 << 0));
 171         } else {
 172                 printk(BIOS_DEBUG,
 173                         "IOAPIC: Enabling interrupts on APIC serial bus\n");
 174                 io_apic_write(ioapic_base, 0x03, 0);
 175         }
 176 }
 177
 178 /**
 179  * Create a new IOAPIC device under the given device.
 180  *
 181  * @param parent      The parent device. A PCI domain or PCI device (in case of PCI IOAPIC).
 182  * @param ioapic_base The IOAPIC base address
 183  * @param gsi_base    Platform specific GSI base
 184  * @return Pointer to the device struct.
 185  */
 186 struct device *ioapic_create_dev(struct device *parent,
 187                                  const uintptr_t ioapic_base,
 188                                  const u32 gsi_base)
 189 {
 190         struct device_path path = {0};
 191         struct device *dev;
 192
 193         if (!parent)
 194                 return NULL;
 195
 196         struct bus *bus = alloc_bus(parent);
 197         if (!bus)
 198                 return NULL;
 199
 200         if (gsi_base == 0)
 201                 register_new_ioapic_gsi0(ioapic_base);
 202         else
 203                 register_new_ioapic(ioapic_base);
 204
 205         path.type = DEVICE_PATH_IOAPIC;
 206         path.ioapic.ioapic_id = get_ioapic_id(ioapic_base);
 207         path.ioapic.addr = ioapic_base;
 208         path.ioapic.gsi_base = gsi_base;
 209
 210         dev = alloc_dev(bus, &path);
 211         assert(dev);
 212
 213         return dev;
 214 }
 215
 216 void setup_ioapic(uintptr_t ioapic_base, u8 ioapic_id)
 217 {
 218         set_ioapic_id(ioapic_base, ioapic_id);
 219         clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1);
 220         route_i8259_irq0(ioapic_base);
 221 }
 222
 223 void register_new_ioapic_gsi0(uintptr_t ioapic_base)
 224 {
 225         setup_ioapic(ioapic_base, 0);
 226 }
 227
 228 void register_new_ioapic(uintptr_t ioapic_base)
 229 {
 230         static u8 ioapic_id;
 231         ioapic_id++;
 232         set_ioapic_id(ioapic_base, ioapic_id);
 233         clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1);
 234 }