src/cpu/intel/haswell/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __CPU_INTEL_HASWELL_CHIP_H__
   4 #define __CPU_INTEL_HASWELL_CHIP_H__
   5
   6 #include <stdbool.h>
   7 #include <stdint.h>
   8
   9 struct cpu_vr_config {
  10         /*
  11          * Minimum voltage for C6/C7 state:
  12          * 0x67 = 1.6V (full swing)
  13          *  ...
  14          * 0x79 = 1.7V
  15          *  ...
  16          * 0x83 = 1.8V (no swing)
  17          */
  18         uint8_t cpu_min_vid;
  19
  20         /*
  21          * Set slow VR ramp rate on C-state exit:
  22          * 0 = Fast VR ramp rate / 2
  23          * 1 = Fast VR ramp rate / 4
  24          * 2 = Fast VR ramp rate / 8
  25          * 3 = Fast VR ramp rate / 16
  26          */
  27         uint8_t slow_ramp_rate_set;
  28
  29         /* Enable slow VR ramp rate */
  30         bool slow_ramp_rate_enable;
  31 };
  32
  33 struct cpu_intel_haswell_config {
  34         int tcc_offset;         /* TCC Activation Offset */
  35
  36         struct cpu_vr_config vr_config;
  37
  38         /* Enable S0iX support */
  39         bool s0ix_enable;
  40 };
  41
  42 #endif /* __CPU_INTEL_HASWELL_CHIP_H__ */