src/cpu/intel/model_106cx/model_106cx_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <cpu/cpu.h>
   6 #include <cpu/x86/msr.h>
   7 #include <cpu/intel/speedstep.h>
   8 #include <cpu/x86/cache.h>
   9 #include <cpu/x86/name.h>
  10
  11 #define HIGHEST_CLEVEL          3
  12 static void configure_c_states(void)
  13 {
  14         msr_t msr;
  15
  16         msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
  17         msr.lo |= (1 << 15); // Lock configuration
  18         msr.lo |= (1 << 10); // redirect IO-based CState transition requests to
  19                              // MWAIT
  20         msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
  21         msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
  22         // TODO Do we want Deep C4 and  Dynamic L2 shrinking?
  23         wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
  24
  25         /* Set Processor MWAIT IO BASE (P_BLK) */
  26         msr.hi = 0;
  27         // TODO Do we want PM1_BASE? Needs SMM?
  28         //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff)
  29         //       << 16);
  30         msr.lo = ((PMB0_BASE + 4) & 0xffff);
  31         wrmsr(MSR_PMG_IO_BASE_ADDR, msr);
  32
  33         /* set C_LVL controls */
  34         msr.hi = 0;
  35         // -2 because LVL0+1 aren't counted
  36         msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16);
  37         wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
  38 }
  39
  40 static void configure_misc(void)
  41 {
  42         msr_t msr;
  43
  44         msr = rdmsr(IA32_MISC_ENABLE);
  45         msr.lo |= (1 << 3);     /* TM1 enable */
  46         msr.lo |= (1 << 13);    /* TM2 enable */
  47         msr.lo |= (1 << 17);    /* Bidirectional PROCHOT# */
  48
  49         msr.lo |= (1 << 10);    /* FERR# multiplexing */
  50
  51         // TODO: Only if  IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
  52         msr.lo |= (1 << 16);    /* Enhanced SpeedStep Enable */
  53
  54         // TODO Do we want Deep C4 and  Dynamic L2 shrinking?
  55         wrmsr(IA32_MISC_ENABLE, msr);
  56
  57         msr.lo |= (1 << 20);    /* Lock Enhanced SpeedStep Enable */
  58         wrmsr(IA32_MISC_ENABLE, msr);
  59 }
  60
  61 static void model_106cx_init(struct device *cpu)
  62 {
  63         char processor_name[49];
  64
  65         /* Print processor name */
  66         fill_processor_name(processor_name);
  67         printk(BIOS_INFO, "CPU: %s.\n", processor_name);
  68
  69         /* Configure C States */
  70         configure_c_states();
  71
  72         /* Configure Enhanced SpeedStep and Thermal Sensors */
  73         configure_misc();
  74
  75         /* TODO: PIC thermal sensor control */
  76 }
  77
  78 static struct device_operations cpu_dev_ops = {
  79         .init     = model_106cx_init,
  80 };
  81
  82 static const struct cpu_device_id cpu_table[] = {
  83         { X86_VENDOR_INTEL, 0x106c0, CPUID_EXACT_MATCH_MASK }, /* Intel Atom 230 */
  84         { X86_VENDOR_INTEL, 0x106ca, CPUID_EXACT_MATCH_MASK }, /* Intel Atom D5xx */
  85         CPU_TABLE_END
  86 };
  87
  88 static const struct cpu_driver driver __cpu_driver = {
  89         .ops      = &cpu_dev_ops,
  90         .id_table = cpu_table,
  91 };