src/cpu/intel/model_206ax/model_206ax.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _CPU_INTEL_MODEL_206AX_H
   4 #define _CPU_INTEL_MODEL_206AX_H
   5
   6 #include <cpu/cpu.h>
   7 #include <stdint.h>
   8
   9 /* SandyBridge CPU stepping */
  10 #define SNB_STEP_B2     2
  11 #define SNB_STEP_C0     3
  12 #define SNB_STEP_D0     5 /* Also J0 */
  13 #define SNB_STEP_D1     6
  14 #define SNB_STEP_D2     7 /* Also J1/Q0 */
  15
  16 /* IvyBridge CPU stepping */
  17 #define IVB_STEP_A0     0
  18 #define IVB_STEP_B0     2
  19 #define IVB_STEP_C0     4
  20 #define IVB_STEP_K0     5
  21 #define IVB_STEP_D0     6
  22 #define IVB_STEP_E0     8
  23 #define IVB_STEP_E1     9
  24
  25 #define IS_SANDY_CPU(x)    ((x & 0xffff0) == 0x206a0)
  26 #define IS_SANDY_CPU_C(x)  ((x & 0xf) == 4)
  27 #define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5)
  28 #define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6)
  29 #define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7)
  30
  31 #define IS_IVY_CPU(x)   ((x & 0xffff0) == 0x306a0)
  32 #define IS_IVY_CPU_C(x) ((x & 0xf) == 4)
  33 #define IS_IVY_CPU_K(x) ((x & 0xf) == 5)
  34 #define IS_IVY_CPU_D(x) ((x & 0xf) == 6)
  35 #define IS_IVY_CPU_E(x) ((x & 0xf) >= 8)
  36
  37 /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
  38 #define SANDYBRIDGE_BCLK                100
  39
  40 #define MSR_CORE_THREAD_COUNT           0x35
  41 #define MSR_FEATURE_CONFIG              0x13c
  42 #define MSR_FLEX_RATIO                  0x194
  43 #define  FLEX_RATIO_LOCK                (1 << 20)
  44 #define  FLEX_RATIO_EN                  (1 << 16)
  45 #define MSR_TEMPERATURE_TARGET          0x1a2
  46 #define MSR_LT_LOCK_MEMORY              0x2e7
  47 #define MSR_PLATFORM_INFO               0xce
  48 #define  PLATFORM_INFO_SET_TDP          (1 << 29)
  49 #define  PLATFORM_INFO_SET_TURBO_LIMIT  (1 << 28)
  50
  51 #define MSR_MISC_PWR_MGMT               0x1aa
  52 #define  MISC_PWR_MGMT_EIST_HW_DIS      (1 << 0)
  53 #define MSR_TURBO_RATIO_LIMIT           0x1ad
  54 #define MSR_POWER_CTL                   0x1fc
  55
  56 #define MSR_PKGC3_IRTL                  0x60a
  57 #define MSR_PKGC6_IRTL                  0x60b
  58 #define MSR_PKGC7_IRTL                  0x60c
  59 #define  IRTL_VALID                     (1 << 15)
  60 #define  IRTL_1_NS                      (0 << 10)
  61 #define  IRTL_32_NS                     (1 << 10)
  62 #define  IRTL_1024_NS                   (2 << 10)
  63 #define  IRTL_32768_NS                  (3 << 10)
  64 #define  IRTL_1048576_NS                (4 << 10)
  65 #define  IRTL_33554432_NS               (5 << 10)
  66 #define  IRTL_RESPONSE_MASK             (0x3ff)
  67
  68 /* long duration in low dword, short duration in high dword */
  69 #define MSR_PKG_POWER_LIMIT             0x610
  70 #define  PKG_POWER_LIMIT_MASK           0x7fff
  71 #define  PKG_POWER_LIMIT_EN             (1 << 15)
  72 #define  PKG_POWER_LIMIT_CLAMP          (1 << 16)
  73 #define  PKG_POWER_LIMIT_TIME_SHIFT     17
  74 #define  PKG_POWER_LIMIT_TIME_MASK      0x7f
  75
  76 #define MSR_PP0_CURRENT_CONFIG          0x601
  77 #define  PP0_CURRENT_LIMIT_LOCK         (1U << 31)
  78 #define  PP0_CURRENT_LIMIT              (112 << 3) /* 112 A */
  79 #define MSR_PP1_CURRENT_CONFIG          0x602
  80 #define  PP1_CURRENT_LIMIT_LOCK         (1U << 31)
  81 #define  PP1_CURRENT_LIMIT_SNB          (35 << 3) /* 35 A */
  82 #define  PP1_CURRENT_LIMIT_IVB          (50 << 3) /* 50 A */
  83 #define MSR_PKG_POWER_SKU_UNIT          0x606
  84 #define MSR_PKG_POWER_SKU               0x614
  85 #define MSR_PP0_POWER_LIMIT             0x638
  86 #define MSR_PP1_POWER_LIMIT             0x640
  87
  88 #define IVB_CONFIG_TDP_MIN_CPUID        0x306a2
  89 #define MSR_CONFIG_TDP_NOMINAL          0x648
  90 #define MSR_CONFIG_TDP_LEVEL1           0x649
  91 #define MSR_CONFIG_TDP_LEVEL2           0x64a
  92 #define MSR_CONFIG_TDP_CONTROL          0x64b
  93 #define MSR_TURBO_ACTIVATION_RATIO      0x64c
  94
  95 /* P-state configuration */
  96 #define PSS_MAX_ENTRIES                 8
  97 #define PSS_RATIO_STEP                  2
  98 #define PSS_LATENCY_TRANSITION          10
  99 #define PSS_LATENCY_BUSMASTER           10
 100
 101 /* Sanity check config options. */
 102 #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE))
 103 # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)"
 104 #endif
 105 #if (CONFIG_SMM_TSEG_SIZE < 0x800000)
 106 # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
 107 #endif
 108 #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
 109 # error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
 110 #endif
 111 #if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0)
 112 # error "CONFIG_IED_REGION_SIZE is not a power of 2"
 113 #endif
 114
 115 /*
 116  * List of supported C-states for Sandy Bridge/Ivy Bridge.
 117  */
 118 enum {
 119         C_STATE_C0              =  0,
 120         C_STATE_C1              =  1,
 121         C_STATE_C1E             =  2,
 122         C_STATE_C3              =  3,
 123         C_STATE_C6              =  4,
 124         C_STATE_C7              =  5,
 125         C_STATE_C7S             =  6,
 126         NUM_C_STATES,
 127 };
 128
 129 /* Lock MSRs */
 130 void intel_model_206ax_finalize_smm(void);
 131
 132 /* Configure power limits for turbo mode */
 133 void set_power_limits(u8 power_limit_1_time);
 134 int cpu_config_tdp_levels(void);
 135
 136 static inline u8 cpu_stepping(void)
 137 {
 138         return cpuid_eax(1) & 0xf;
 139 }
 140
 141 #endif