src/cpu/intel/smm/gen1/smmrelocate.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* SMM relocation for i945-ivybridge. */
   4
   5 #include <assert.h>
   6 #include <types.h>
   7 #include <string.h>
   8 #include <device/device.h>
   9 #include <device/pci.h>
  10 #include <commonlib/helpers.h>
  11 #include <cpu/x86/mp.h>
  12 #include <cpu/x86/msr.h>
  13 #include <cpu/x86/mtrr.h>
  14 #include <cpu/x86/smm.h>
  15 #include <cpu/intel/em64t101_save_state.h>
  16 #include <cpu/intel/smm_reloc.h>
  17 #include <console/console.h>
  18 #include <smp/node.h>
  19
  20 #define SMRR_SUPPORTED (1 << 11)
  21
  22 #define  D_OPEN         (1 << 6)
  23 #define  D_CLS          (1 << 5)
  24 #define  D_LCK          (1 << 4)
  25 #define  G_SMRAME       (1 << 3)
  26 #define  C_BASE_SEG     ((0 << 2) | (1 << 1) | (0 << 0))
  27
  28 /* On model_6fx, model_1067x and model_106cx SMRR functions slightly
  29    differently. The MSR are at different location from the rest
  30    and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
  31 bool cpu_has_alternative_smrr(void)
  32 {
  33         struct cpuinfo_x86 c;
  34         get_fms(&c, cpuid_eax(1));
  35         if (c.x86 != 6)
  36                 return false;
  37         switch (c.x86_model) {
  38         case 0xf:
  39         case 0x17: /* core2 */
  40         case 0x1c: /* Bonnell */
  41                 return true;
  42         default:
  43                 return false;
  44         }
  45 }
  46
  47 static void write_smrr_alt(struct smm_relocation_params *relo_params)
  48 {
  49         msr_t msr;
  50         msr = rdmsr(IA32_FEATURE_CONTROL);
  51         /* SMRR enabled and feature locked */
  52         if (!((msr.lo & SMRR_ENABLE)
  53                         && (msr.lo & FEATURE_CONTROL_LOCK_BIT))) {
  54                 printk(BIOS_WARNING,
  55                         "SMRR not enabled, skip writing SMRR...\n");
  56                 return;
  57         }
  58
  59         printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
  60                relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
  61
  62         wrmsr(CORE2_SMRR_PHYS_BASE, relo_params->smrr_base);
  63         wrmsr(CORE2_SMRR_PHYS_MASK, relo_params->smrr_mask);
  64 }
  65
  66 static void fill_in_relocation_params(struct smm_relocation_params *params)
  67 {
  68         uintptr_t tseg_base;
  69         size_t tseg_size;
  70
  71         /* All range registers are aligned to 4KiB */
  72         const u32 rmask = ~((1 << 12) - 1);
  73
  74         smm_region(&tseg_base, &tseg_size);
  75
  76         if (!IS_ALIGNED(tseg_base, tseg_size)) {
  77                 printk(BIOS_WARNING,
  78                        "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
  79                 return;
  80         }
  81
  82         /* SMRR has 32-bits of valid address aligned to 4KiB. */
  83         params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
  84         params->smrr_base.hi = 0;
  85         params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
  86         params->smrr_mask.hi = 0;
  87
  88         /* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */
  89         if (cpu_has_alternative_smrr())
  90                 params->smrr_base.lo &= rmask;
  91
  92         smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
  93 }
  94
  95 static void setup_ied_area(struct smm_relocation_params *params)
  96 {
  97         char *ied_base;
  98
  99         struct ied_header ied = {
 100                 .signature = "INTEL RSVD",
 101                 .size = params->ied_size,
 102                 .reserved = {0},
 103         };
 104
 105         ied_base = (void *)params->ied_base;
 106
 107         /* Place IED header at IEDBASE. */
 108         memcpy(ied_base, &ied, sizeof(ied));
 109
 110         /* Zero out 32KiB at IEDBASE + 1MiB */
 111         memset(ied_base + (1 << 20), 0, (32 << 10));
 112 }
 113
 114 void smm_lock(void)
 115 {
 116         /* LOCK the SMM memory window and enable normal SMM.
 117          * After running this function, only a full reset can
 118          * make the SMM registers writable again.
 119          */
 120         printk(BIOS_DEBUG, "Locking SMM.\n");
 121
 122         northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG);
 123 }
 124
 125 void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 126                 size_t *smm_save_state_size)
 127 {
 128         printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
 129
 130         fill_in_relocation_params(&smm_reloc_params);
 131
 132         smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
 133
 134         if (smm_reloc_params.ied_size)
 135                 setup_ied_area(&smm_reloc_params);
 136
 137         /* This may not be correct for older CPU's supported by this code,
 138            but given that em64t101_smm_state_save_area_t is larger than the
 139            save_state of these CPU's it works. */
 140         *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
 141 }
 142
 143 void smm_initialize(void)
 144 {
 145         /* Clear the SMM state in the southbridge. */
 146         smm_southbridge_clear_state();
 147
 148         /*
 149          * Run the relocation handler for on the BSP to check and set up
 150          * parallel SMM relocation.
 151          */
 152         smm_initiate_relocation();
 153 }
 154
 155 /* The relocation work is actually performed in SMM context, but the code
 156  * resides in the ramstage module. This occurs by trampolining from the default
 157  * SMRAM entry point to here. */
 158 void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
 159                                 uintptr_t staggered_smbase)
 160 {
 161         msr_t mtrr_cap;
 162         struct smm_relocation_params *relo_params = &smm_reloc_params;
 163         /* The em64t101 save state is sufficiently compatible with older
 164            save states with regards of smbase, smm_revision. */
 165         em64t101_smm_state_save_area_t *save_state;
 166         u32 smbase = staggered_smbase;
 167         u32 iedbase = relo_params->ied_base;
 168
 169         printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
 170
 171         /* Make appropriate changes to the save state map. */
 172         if (relo_params->ied_size)
 173                 printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
 174                        smbase, iedbase);
 175         else
 176                 printk(BIOS_DEBUG, "New SMBASE=0x%08x\n",
 177                        smbase);
 178
 179         save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
 180                         sizeof(*save_state));
 181         save_state->smbase = smbase;
 182
 183         printk(BIOS_SPEW, "SMM revision: 0x%08x\n", save_state->smm_revision);
 184         if (save_state->smm_revision == 0x00030101)
 185                 save_state->iedbase = iedbase;
 186
 187         /* Write EMRR and SMRR MSRs based on indicated support. */
 188         mtrr_cap = rdmsr(MTRR_CAP_MSR);
 189         if (!(mtrr_cap.lo & SMRR_SUPPORTED))
 190                 return;
 191
 192         if (cpu_has_alternative_smrr())
 193                 write_smrr_alt(relo_params);
 194         else
 195                 write_smrr(relo_params);
 196 }
 197
 198 /*
 199  * The default SMM entry can happen in parallel or serially. If the
 200  * default SMM entry is done in parallel the BSP has already setup
 201  * the saving state to each CPU's MSRs. At least one save state size
 202  * is required for the initial SMM entry for the BSP to determine if
 203  * parallel SMM relocation is even feasible.
 204  */
 205 void smm_relocate(void)
 206 {
 207         /*
 208          * If smm_save_state_in_msrs is non-zero then parallel SMM relocation
 209          * shall take place. Run the relocation handler a second time on the
 210          * BSP to do the final move. For APs, a relocation handler always
 211          * needs to be run.
 212          */
 213         if (!boot_cpu())
 214                 smm_initiate_relocation();
 215 }