src/cpu/x86/mtrr/earlymtrr.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <cpu/cpu.h>
   4 #include <cpu/x86/mtrr.h>
   5 #include <cpu/x86/msr.h>
   6 #include <console/console.h>
   7 #include <commonlib/bsd/helpers.h>
   8 #include <types.h>
   9
  10 /* Get first available variable MTRR.
  11  * Returns var# if available, else returns -1.
  12  */
  13 int get_free_var_mtrr(void)
  14 {
  15         msr_t maskm;
  16         int vcnt;
  17         int i;
  18
  19         vcnt = get_var_mtrr_count();
  20
  21         /* Identify the first var mtrr which is not valid. */
  22         for (i = 0; i < vcnt; i++) {
  23                 maskm = rdmsr(MTRR_PHYS_MASK(i));
  24                 if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
  25                         return i;
  26         }
  27
  28         /* No free var mtrr. */
  29         return -1;
  30 }
  31
  32 void set_var_mtrr(
  33         unsigned int reg, unsigned int base, unsigned int size,
  34         unsigned int type)
  35 {
  36         /* Bit 32-35 of MTRRphysMask should be set to 1 */
  37         /* FIXME: It only support 4G less range */
  38         msr_t basem, maskm;
  39
  40         if (type == MTRR_TYPE_WRBACK && !is_cache_sets_power_of_two() && ENV_CACHE_AS_RAM)
  41                 printk(BIOS_ERR, "MTRR Error: Type %x may not be supported due to NEM limitation\n",
  42                          type);
  43         if (!IS_POWER_OF_2(size))
  44                 printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size);
  45         if (size < 4 * KiB)
  46                 printk(BIOS_ERR, "MTRR Error: size %#x smaller than 4KiB\n", size);
  47         if (base % size != 0)
  48                 printk(BIOS_ERR, "MTRR Error: base %#x must be aligned to size %#x\n", base,
  49                        size);
  50
  51         basem.lo = base | type;
  52         basem.hi = 0;
  53         wrmsr(MTRR_PHYS_BASE(reg), basem);
  54         maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
  55         maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
  56         wrmsr(MTRR_PHYS_MASK(reg), maskm);
  57 }
  58
  59 void clear_all_var_mtrr(void)
  60 {
  61         msr_t mtrr = { .raw = 0 };
  62         int vcnt;
  63         int i;
  64
  65         vcnt = get_var_mtrr_count();
  66
  67         for (i = 0; i < vcnt; i++) {
  68                 wrmsr(MTRR_PHYS_MASK(i), mtrr);
  69                 wrmsr(MTRR_PHYS_BASE(i), mtrr);
  70         }
  71 }
  72
  73 void var_mtrr_context_init(struct var_mtrr_context *ctx)
  74 {
  75         ctx->max_var_mtrrs = get_var_mtrr_count();
  76         ctx->used_var_mtrrs = 0;
  77 }
  78
  79 int var_mtrr_set(struct var_mtrr_context *ctx, uintptr_t addr, size_t size, int type)
  80 {
  81         const uint32_t upper_mask = (1U << (cpu_phys_address_size() - 32)) - 1;
  82         /* Utilize additional MTRRs if the specified size is greater than the
  83            base address alignment. */
  84         while (size != 0) {
  85                 uint32_t addr_lsb;
  86                 uint32_t size_msb;
  87                 uint32_t mtrr_size;
  88                 msr_t base;
  89                 msr_t mask;
  90
  91                 if (ctx->used_var_mtrrs >= ctx->max_var_mtrrs) {
  92                         printk(BIOS_ERR, "No more variable MTRRs: %d\n",
  93                                         ctx->max_var_mtrrs);
  94                         return -1;
  95                 }
  96
  97                 addr_lsb = __ffs(addr);
  98                 size_msb = __fls(size);
  99
 100                 /* All MTRR entries need to have their base aligned to the mask
 101                    size. The maximum size is calculated by a function of the
 102                    min base bit set and maximum size bit set. */
 103                 if (addr_lsb > size_msb)
 104                         mtrr_size = 1 << size_msb;
 105                 else
 106                         mtrr_size = 1 << addr_lsb;
 107
 108                 base.hi = (uint64_t)addr >> 32;
 109                 base.lo = addr | type;
 110                 mask.hi = upper_mask;
 111                 mask.lo = ~(mtrr_size - 1) | MTRR_PHYS_MASK_VALID;
 112                 ctx->mtrr[ctx->used_var_mtrrs].base = base;
 113                 ctx->mtrr[ctx->used_var_mtrrs].mask = mask;
 114                 ctx->used_var_mtrrs++;
 115
 116                 size -= mtrr_size;
 117                 addr += mtrr_size;
 118         }
 119
 120         return 0;
 121 }
 122
 123 /* Romstage sets up a MTRR context in cbmem and sets up this pointer in postcar stage. */
 124 __attribute__((used, __section__(".module_parameters"))) const volatile uintptr_t post_car_mtrrs;
 125
 126 void commit_mtrr_setup(const struct var_mtrr_context *ctx)
 127 {
 128         clear_all_var_mtrr();
 129
 130         for (int i = 0; i < ctx->used_var_mtrrs; i++) {
 131                 wrmsr(MTRR_PHYS_BASE(i), ctx->mtrr[i].base);
 132                 wrmsr(MTRR_PHYS_MASK(i), ctx->mtrr[i].mask);
 133         }
 134         /* Enable MTRR */
 135         msr_t mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR);
 136         mtrr_def_type.lo &= MTRR_DEF_TYPE_MASK;
 137         mtrr_def_type.lo |= MTRR_DEF_TYPE_EN;
 138         wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type);
 139 }
 140
 141 void postcar_mtrr_setup(void)
 142 {
 143         commit_mtrr_setup((const struct var_mtrr_context *)post_car_mtrrs);
 144 }