src/drivers/net/ns8390.h

   1 /* SPDX-License-Identifier: BSD-2-Clause */
   2
   3 /**************************************************************************
   4 ETHERBOOT -  BOOTP/TFTP Bootstrap Program
   5
   6 Author: Martin Renters
   7   Date: Jun/94
   8
   9 **************************************************************************/
  10
  11 #define VENDOR_NONE     0
  12 #define VENDOR_WD       1
  13 #define VENDOR_NOVELL   2
  14 #define VENDOR_3COM     3
  15
  16 #define FLAG_PIO        0x01
  17 #define FLAG_16BIT      0x02
  18 #define FLAG_790        0x04
  19
  20 #define MEM_8192        32
  21 #define MEM_16384       64
  22 #define MEM_32768       128
  23
  24 #define ISA_MAX_ADDR    0x400
  25
  26 /**************************************************************************
  27 NE1000/2000 definitions
  28 **************************************************************************/
  29 #define NE_ASIC_OFFSET  0x10
  30 #define NE_RESET        0x0F            /* Used to reset card */
  31 #define NE_DATA         0x00            /* Used to read/write NIC mem */
  32
  33 #define COMPEX_RL2000_TRIES     200
  34
  35 /**************************************************************************
  36 8390 Register Definitions
  37 **************************************************************************/
  38 #define D8390_P0_COMMAND        0x00
  39 #define D8390_P0_PSTART         0x01
  40 #define D8390_P0_PSTOP          0x02
  41 #define D8390_P0_BOUND          0x03
  42 #define D8390_P0_TSR            0x04
  43 #define D8390_P0_TPSR           0x04
  44 #define D8390_P0_TBCR0          0x05
  45 #define D8390_P0_TBCR1          0x06
  46 #define D8390_P0_ISR            0x07
  47 #define D8390_P0_RSAR0          0x08
  48 #define D8390_P0_RSAR1          0x09
  49 #define D8390_P0_RBCR0          0x0A
  50 #define D8390_P0_RBCR1          0x0B
  51 #define D8390_P0_RSR            0x0C
  52 #define D8390_P0_RCR            0x0C
  53 #define D8390_P0_TCR            0x0D
  54 #define D8390_P0_DCR            0x0E
  55 #define D8390_P0_IMR            0x0F
  56 #define D8390_P1_COMMAND        0x00
  57 #define D8390_P1_PAR0           0x01
  58 #define D8390_P1_PAR1           0x02
  59 #define D8390_P1_PAR2           0x03
  60 #define D8390_P1_PAR3           0x04
  61 #define D8390_P1_PAR4           0x05
  62 #define D8390_P1_PAR5           0x06
  63 #define D8390_P1_CURR           0x07
  64 #define D8390_P1_MAR0           0x08
  65
  66 #define D8390_COMMAND_PS0       0x0             /* Page 0 select */
  67 #define D8390_COMMAND_PS1       0x40            /* Page 1 select */
  68 #define D8390_COMMAND_PS2       0x80            /* Page 2 select */
  69 #define D8390_COMMAND_RD2       0x20            /* Remote DMA control */
  70 #define D8390_COMMAND_RD1       0x10
  71 #define D8390_COMMAND_RD0       0x08
  72 #define D8390_COMMAND_TXP       0x04            /* transmit packet */
  73 #define D8390_COMMAND_STA       0x02            /* start */
  74 #define D8390_COMMAND_STP       0x01            /* stop */
  75
  76 #define D8390_RCR_MON           0x20            /* monitor mode */
  77
  78 #define D8390_DCR_FT1           0x40
  79 #define D8390_DCR_LS            0x08            /* Loopback select */
  80 #define D8390_DCR_WTS           0x01            /* Word transfer select */
  81
  82 #define D8390_ISR_PRX           0x01            /* successful recv */
  83 #define D8390_ISR_PTX           0x02            /* successful xmit */
  84 #define D8390_ISR_RXE           0x04            /* receive error */
  85 #define D8390_ISR_TXE           0x08            /* transmit error */
  86 #define D8390_ISR_OVW           0x10            /* Overflow */
  87 #define D8390_ISR_CNT           0x20            /* Counter overflow */
  88 #define D8390_ISR_RDC           0x40            /* Remote DMA complete */
  89 #define D8390_ISR_RST           0x80            /* reset */
  90
  91 #define D8390_RSTAT_PRX         0x01            /* successful recv */
  92 #define D8390_RSTAT_CRC         0x02            /* CRC error */
  93 #define D8390_RSTAT_FAE         0x04            /* Frame alignment error */
  94 #define D8390_RSTAT_OVER        0x08            /* FIFO overrun */
  95
  96 #define D8390_TXBUF_SIZE        6
  97 #define D8390_RXBUF_END         32
  98 #define D8390_PAGE_SIZE         256
  99
 100 struct ringbuffer {
 101         unsigned char status;
 102         unsigned char next;
 103         unsigned short len;
 104 };
 105 /*
 106  * Local variables:
 107  *  c-basic-offset: 8
 108  * End:
 109  */