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soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git]
/
src
/
ec
/
compal
/
ene932
/
chip.h
blob
d91af167abbe1d9a364c1657b1ea79baf5dce211
1
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _EC_COMPAL_ENE932_CHIP_H
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#define _EC_COMPAL_ENE932_CHIP_H
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struct
ec_compal_ene932_config
{
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};
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#endif
/* _EC_COMPAL_ENE932_CHIP_H */