src/include/cpu/intel/em64t100_save_state.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __EM64T100_SAVE_STATE_H__
   4 #define __EM64T100_SAVE_STATE_H__
   5
   6 #include <types.h>
   7 #include <cpu/x86/smm.h>
   8
   9 /* Intel Revision 30100 SMM State-Save Area */
  10
  11 #define SMM_EM64T100_ARCH_OFFSET 0x7c00
  12 #define SMM_EM64T100_SAVE_STATE_OFFSET \
  13         SMM_SAVE_STATE_BEGIN(SMM_EM64T100_ARCH_OFFSET)
  14 typedef struct {
  15         u8      reserved0[256];
  16         u8      reserved1[208];
  17
  18         u32     gdtr_upper_base;
  19         u32     ldtr_upper_base;
  20         u32     idtr_upper_base;
  21
  22         u8      reserved2[4];
  23
  24         u64     io_rdi;
  25         u64     io_rip;
  26         u64     io_rcx;
  27         u64     io_rsi;
  28
  29         u8      reserved3[64];
  30         u32     cr4;
  31
  32         u8      reserved4[72];
  33
  34         u32     gdtr_base;
  35         u8      reserved5[4];
  36         u32     idtr_base;
  37         u8      reserved6[4];
  38         u32     ldtr_base;
  39
  40         u8      reserved7[88];
  41
  42         u32     smbase;
  43         u32     smm_revision;
  44
  45         u16     io_restart;
  46         u16     autohalt_restart;
  47
  48         u8      reserved8[24];
  49
  50         u64     r15;
  51         u64     r14;
  52         u64     r13;
  53         u64     r12;
  54         u64     r11;
  55         u64     r10;
  56         u64     r9;
  57         u64     r8;
  58
  59         u64     rax;
  60         u64     rcx;
  61         u64     rdx;
  62         u64     rbx;
  63
  64         u64     rsp;
  65         u64     rbp;
  66         u64     rsi;
  67         u64     rdi;
  68
  69         u64     io_mem_addr;
  70         u32     io_misc_info;
  71
  72         u32     es_sel;
  73         u32     cs_sel;
  74         u32     ss_sel;
  75         u32     ds_sel;
  76         u32     fs_sel;
  77         u32     gs_sel;
  78
  79         u32     ldtr_sel;
  80         u32     tr_sel;
  81
  82         u64     dr7;
  83         u64     dr6;
  84         u64     rip;
  85         u64     efer;
  86         u64     rflags;
  87
  88         u64     cr3;
  89         u64     cr0;
  90 } __packed em64t100_smm_state_save_area_t;
  91
  92 #endif