src/include/cpu/intel/l2_cache.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /* The L2 cache definitions here only apply to SECC/SECC2 P6 family CPUs
   4  * with Klamath (63x), Deschutes (65x) and Katmai (67x) cores.
   5  * It is not required for Coppermine (68x) and Tualatin (6bx) cores.
   6  * It is currently not known if Celerons with Mendocino core require
   7  * the special initialization.
   8  * Covington-core Celerons do not have L2 cache.
   9  */
  10
  11 /* This is a straight port from coreboot v1. */
  12
  13 #ifndef __P6_L2_CACHE_H
  14 #define __P6_L2_CACHE_H
  15
  16 #include <stdint.h>
  17
  18 #define EBL_CR_POWERON  0x2A
  19
  20 #define BBL_CR_D0       0x88
  21 #define BBL_CR_D1       0x89
  22 #define BBL_CR_D2       0x8A
  23 #define BBL_CR_D3       0x8B
  24
  25 #define BBL_CR_ADDR     0x116
  26 #define BBL_CR_DECC     0x118
  27 #define BBL_CR_CTL      0x119
  28 #define BBL_CR_TRIG     0x11A
  29 #define BBL_CR_BUSY     0x11B
  30 #define BBL_CR_CTL3     0x11E
  31
  32 #define BBLCR3_L2_CONFIGURED       (1<<0)
  33 /* bits [4:1] */
  34 #define BBLCR3_L2_LATENCY          0x1e
  35 #define BBLCR3_L2_ECC_CHECK_ENABLE (1<<5)
  36 #define BBLCR3_L2_ADDR_PARITY_ENABLE (1<<6)
  37 #define BBLCR3_L2_CRTN_PARITY_ENABLE (1<<7)
  38 #define BBLCR3_L2_ENABLED          (1<<8)
  39 /* bits [17:13] */
  40 #define BBLCR3_L2_SIZE             (0x1f << 13)
  41 #define BBLCR3_L2_SIZE_256K        (0x01 << 13)
  42 #define BBLCR3_L2_SIZE_512K        (0x02 << 13)
  43 #define BBLCR3_L2_SIZE_1M          (0x04 << 13)
  44 #define BBLCR3_L2_SIZE_2M          (0x08 << 13)
  45 #define BBLCR3_L2_SIZE_4M          (0x10 << 13)
  46 /* bits [22:20] */
  47 #define BBLCR3_L2_PHYSICAL_RANGE   (0x7 << 20)
  48 /* TODO: This bitmask does not agree with Intel's documentation.
  49  * Get confirmation one way or another.
  50  */
  51 #define BBLCR3_L2_SUPPLIED_ECC     0x40000
  52
  53 #define BBLCR3_L2_HARDWARE_DISABLE (1<<23)
  54 /* Also known as... */
  55 #define BBLCR3_L2_NOT_PRESENT      (1<<23)
  56
  57 /* L2 commands */
  58 #define L2CMD_RLU 0x0c /* 01100 Data read w/ LRU update */
  59 #define L2CMD_TRR 0x0e /* 01110 Tag read with data read */
  60 #define L2CMD_TI  0x0f /* 01111 Tag inquiry */
  61 #define L2CMD_CR  0x02 /* 00010 L2 control register read */
  62 #define L2CMD_CW  0x03 /* 00011 L2 control register write */
  63 #define L2CMD_TWR 0x08 /* 010-- Tag read w/ data read */
  64 #define L2CMD_TWW 0x1c /* 111-- Tag write w/ data write */
  65 #define L2CMD_TW  0x10 /* 100-- Tag write */
  66 /* MESI encode for L2 commands above */
  67 #define L2CMD_MESI_M 3
  68 #define L2CMD_MESI_E 2
  69 #define L2CMD_MESI_S 1
  70 #define L2CMD_MESI_I 0
  71
  72 int calculate_l2_latency(void);
  73 int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way,
  74         u8 command);
  75 int read_l2(u32 address);
  76 int write_l2(u32 address, u32 data);
  77 int test_l2_address_alias(u32 address1, u32 address2, u32 data_high,
  78         u32 data_low);
  79 int calculate_l2_cache_size(void);
  80 int calculate_l2_physical_address_range(void);
  81 int set_l2_ecc(void);
  82
  83 int p6_configure_l2_cache(void);
  84
  85 #endif /* __P6_L2_CACHE_H */