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drivers/asmedia: Add code to enable AHCI for ASM1061
[coreboot2.git] / src / include / cpu / x86 / msr.h
bloba5226fb0b69aaa77cdf44b64efc4fdbf5c95f4e7
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef CPU_X86_MSR_H
4 #define CPU_X86_MSR_H
5
6 #include <cpu/x86/msr_access.h> /* IWYU pragma: export */
7
8 /* Intel SDM: Table 2-1
9 * IA-32 architectural MSR: Extended Feature Enable Register
10 *
11 * AMD64 Programmers Manual vol2 Revision 3.30 and/or the device's BKDG
12 */
13
14 #define IA32_EFER 0xC0000080
15 #define EFER_NXE (1 << 11)
16 #define EFER_LMA (1 << 10)
17 #define EFER_LME (1 << 8)
18 #define EFER_SCE (1 << 0)
19
20 /* Page attribute type MSR */
21 #define TSC_MSR 0x10
22 #define IA32_PLATFORM_ID 0x17
23 #define IA32_APIC_BASE_MSR_INDEX 0x1B
24 #define IA32_FEATURE_CONTROL 0x3a
25 #define FEATURE_CONTROL_LOCK_BIT (1 << 0)
26 #define FEATURE_ENABLE_VMX (1 << 2)
27 #define SMRR_ENABLE (1 << 3)
28 #define CPUID_VMX (1 << 5)
29 #define CPUID_SMX (1 << 6)
30 #define CPUID_DCA (1 << 18)
31 #define CPUID_X2APIC (1 << 21)
32 #define CPUID_AES (1 << 25)
33 #define SGX_GLOBAL_ENABLE (1 << 18)
34 #define PLATFORM_INFO_SET_TDP (1 << 29)
35 #define IA32_BIOS_UPDT_TRIG 0x79
36 #define IA32_BIOS_SIGN_ID 0x8b
37 #define IA32_MPERF 0xe7
38 #define IA32_APERF 0xe8
39 /* STM */
40 #define IA32_SMM_MONITOR_CTL_MSR 0x9B
41 #define SMBASE_RO_MSR 0x98
42 #define IA32_SMM_MONITOR_VALID (1 << 0)
43 #define IA32_MCG_CAP 0x179
44 #define MCG_CTL_P (1 << 8)
45 #define MCA_BANKS_MASK 0xff
46 #define IA32_PERF_STATUS 0x198
47 #define IA32_PERF_CTL 0x199
48 #define IA32_THERM_INTERRUPT 0x19b
49 #define IA32_MISC_ENABLE 0x1a0
50 #define FAST_STRINGS_ENABLE_BIT (1 << 0)
51 #define TM1_TM2_EMTTM_ENABLE_BIT (1 << 3)
52 #define SPEED_STEP_ENABLE_BIT (1 << 16)
53 #define IA32_ENERGY_PERF_BIAS 0x1b0
54 #define ENERGY_POLICY_PERFORMANCE 0
55 #define ENERGY_POLICY_NORMAL 6
56 #define ENERGY_POLICY_POWERSAVE 15
57 #define ENERGY_POLICY_MASK 0xf
58 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
59 #define CRITICAL_TEMP_INTERRUPT_ENABLE (1 << 4)
60 #define SMRR_PHYSBASE_MSR 0x1F2
61 #define SMRR_PHYSMASK_MSR 0x1F3
62 #define IA32_PLATFORM_DCA_CAP 0x1f8
63 #define DCA_TYPE0_EN (1 << 0)
64 #define IA32_PAT 0x277
65 #define IA32_MC0_CTL 0x400
66 #define IA32_MC_CTL(bank) (IA32_MC0_CTL + 4 * (bank))
67 #define IA32_MC0_STATUS 0x401
68 #define IA32_MC_STATUS(bank) (IA32_MC0_STATUS + 4 * (bank))
69 #define MCA_STATUS_HI_VAL (1UL << (63 - 32))
70 #define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32))
71 #define MCA_STATUS_HI_UC (1UL << (61 - 32))
72 #define MCA_STATUS_HI_EN (1UL << (60 - 32))
73 #define MCA_STATUS_HI_MISCV (1UL << (59 - 32))
74 #define MCA_STATUS_HI_ADDRV (1UL << (58 - 32))
75 #define MCA_STATUS_HI_PCC (1UL << (57 - 32))
76 #define MCA_STATUS_HI_COREID_VAL (1UL << (56 - 32))
77 #define MCA_STATUS_HI_CECC (1UL << (46 - 32))
78 #define MCA_STATUS_HI_UECC (1UL << (45 - 32))
79 #define MCA_STATUS_HI_DEFERRED (1UL << (44 - 32))
80 #define MCA_STATUS_HI_POISON (1UL << (43 - 32))
81 #define MCA_STATUS_HI_SUBLINK (1UL << (41 - 32))
82 #define MCA_STATUS_HI_ERRCOREID_MASK (0xf << 0)
83 #define MCA_STATUS_LO_ERRCODE_EXT_SH 16
84 #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
85 #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
86 #define IA32_LT_UNLOCK_MEMORY 0x2e6
87 #define IA32_MC0_ADDR 0x402
88 #define IA32_MC_ADDR(bank) (IA32_MC0_ADDR + 4 * (bank))
89 #define IA32_MC0_MISC 0x403
90 #define IA32_MC_MISC(bank) (IA32_MC0_MISC + 4 * (bank))
91 #define IA32_VMX_BASIC_MSR 0x480
92 #define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32))
93 #define IA32_VMX_MISC_MSR 0x485
94
95 #define IA32_PM_ENABLE 0x770
96 #define HWP_ENABLE 0x1
97 #define IA32_HWP_CAPABILITIES 0x771
98 #define IA32_HWP_REQUEST 0x774
99 #define IA32_HWP_REQUEST_EPP_MASK 0xff000000
100 #define IA32_HWP_REQUEST_EPP_SHIFT 24
101 #define IA32_HWP_STATUS 0x777
102 #define IA32_L3_PROTECTED_WAYS 0xc85
103 #define IA32_SF_QOS_INFO 0xc87
104 #define IA32_SF_WAY_COUNT_MASK 0x3f
105 #define IA32_PQR_ASSOC 0xc8f
106 /* MSR bits 33:32 encode slot number 0-3 */
107 #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)
108 #define IA32_L3_MASK_1 0xc91
109 #define IA32_L3_MASK_2 0xc92
110
111 #define IA32_CR_SF_QOS_MASK_1 0x1891
112 #define IA32_CR_SF_QOS_MASK_2 0x1892
113
114 #ifndef __ASSEMBLER__
115
116 typedef struct msrinit_struct {
117 unsigned int index;
118 msr_t msr;
119 } msrinit_t;
120
121 /* Get MCA bank count from MSR */
122 static inline unsigned int mca_get_bank_count(void)
123 {
124 msr_t msr = rdmsr(IA32_MCG_CAP);
125 return msr.lo & MCA_BANKS_MASK;
126 }
127
128 /* Clear all MCA status registers */
129 static inline void mca_clear_status(void)
130 {
131 const unsigned int num_banks = mca_get_bank_count();
132 const msr_t msr = {.lo = 0, .hi = 0};
133
134 for (unsigned int i = 0 ; i < num_banks ; i++)
135 wrmsr(IA32_MC_STATUS(i), msr);
136 }
137
138 /* Helpers for interpreting MC[i]_STATUS */
139
140 static inline int mca_valid(msr_t msr)
141 {
142 return !!(msr.hi & MCA_STATUS_HI_VAL);
143 }
144
145 static inline int mca_over(msr_t msr)
146 {
147 return !!(msr.hi & MCA_STATUS_HI_OVERFLOW);
148 }
149
150 static inline int mca_uc(msr_t msr)
151 {
152 return !!(msr.hi & MCA_STATUS_HI_UC);
153 }
154
155 static inline int mca_en(msr_t msr)
156 {
157 return !!(msr.hi & MCA_STATUS_HI_EN);
158 }
159
160 static inline int mca_miscv(msr_t msr)
161 {
162 return !!(msr.hi & MCA_STATUS_HI_MISCV);
163 }
164
165 static inline int mca_addrv(msr_t msr)
166 {
167 return !!(msr.hi & MCA_STATUS_HI_ADDRV);
168 }
169
170 static inline int mca_pcc(msr_t msr)
171 {
172 return !!(msr.hi & MCA_STATUS_HI_PCC);
173 }
174
175 static inline int mca_idv(msr_t msr)
176 {
177 return !!(msr.hi & MCA_STATUS_HI_COREID_VAL);
178 }
179
180 static inline int mca_cecc(msr_t msr)
181 {
182 return !!(msr.hi & MCA_STATUS_HI_CECC);
183 }
184
185 static inline int mca_uecc(msr_t msr)
186 {
187 return !!(msr.hi & MCA_STATUS_HI_UECC);
188 }
189
190 static inline int mca_defd(msr_t msr)
191 {
192 return !!(msr.hi & MCA_STATUS_HI_DEFERRED);
193 }
194
195 static inline int mca_poison(msr_t msr)
196 {
197 return !!(msr.hi & MCA_STATUS_HI_POISON);
198 }
199
200 static inline int mca_sublink(msr_t msr)
201 {
202 return !!(msr.hi & MCA_STATUS_HI_SUBLINK);
203 }
204
205 static inline uint16_t mca_err_code(msr_t reg)
206 {
207 return reg.lo & MCA_STATUS_LO_ERRCODE_MASK;
208 }
209
210 static inline uint16_t mca_err_extcode(msr_t reg)
211 {
212 return reg.lo & MCA_STATUS_LO_ERRCODE_EXT_MASK;
213 }
214
215 /* Machine Check errors may be categorized by type, as determined by the
216 * Error Code field of MC[i]_STATUS. The definitions below can typically
217 * be found by searching the BKDG for a table called "Error Code Types".
218 */
219 /* TLB Errors 0000 0000 0001 TTLL */
220 #define MCA_ERRCODE_TLB_DETECT 0xfff0
221 #define MCA_ERRCODE_TLB_TT_SH 2 /* Transaction Type */
222 #define MCA_ERRCODE_TLB_TT_MASK (0x3 << MCA_ERRCODE_TLB_TT_SH)
223 #define MCA_ERRCODE_TLB_LL_SH 0 /* Cache Level */
224 #define MCA_ERRCODE_TLB_LL_MASK (0x3 << MCA_ERRCODE_TLB_LL_SH)
225
226 /* Memory Errors 0000 0001 RRRR TTLL */
227 #define MCA_ERRCODE_MEM_DETECT 0xff00
228 #define MCA_ERRCODE_MEM_RRRR_SH 4 /* Memory Transaction Type */
229 #define MCA_ERRCODE_MEM_RRRR_MASK (0xf << MCA_ERRCODE_MEM_RRRR_MASK)
230 #define MCA_ERRCODE_MEM_TT_SH 2 /* Transaction Type */
231 #define MCA_ERRCODE_MEM_TT_MASK (0x3 << MCA_ERRCODE_MEM_TT_SH)
232 #define MCA_ERRCODE_MEM_LL_SH 0 /* Cache Level */
233 #define MCA_ERRCODE_MEM_LL_MASK (0x3 << MCA_ERRCODE_MEM_LL_SH)
234
235 /* Bus Errors 0000 1PPT RRRR IILL */
236 #define MCA_ERRCODE_BUS_DETECT 0xf800
237 #define MCA_ERRCODE_BUS_PP_SH 9 /* Participation Processor */
238 #define MCA_ERRCODE_BUS_PP_MASK (0x3 << MCA_ERRCODE_BUS_PP_SH)
239 #define MCA_ERRCODE_BUS_T_SH 8 /* Timeout */
240 #define MCA_ERRCODE_BUS_T_MASK (0x1 << MCA_ERRCODE_BUS_T_SH)
241 #define MCA_ERRCODE_BUS_RRRR_SH 4 /* Memory Transaction Type */
242 #define MCA_ERRCODE_BUS_RRRR_MASK (0xf << MCA_ERRCODE_BUS_RRRR_SH)
243 #define MCA_ERRCODE_BUS_II_SH 2 /* Memory or IO */
244 #define MCA_ERRCODE_BUS_II_MASK (0x3 << MCA_ERRCODE_BUS_II_SH)
245 #define MCA_ERRCODE_BUS_LL_SH 0 /* Cache Level */
246 #define MCA_ERRCODE_BUS_LL_MASK (0x3 << MCA_ERRCODE_BUS_LL_SH)
247
248 /* Int. Unclassified Errors 0000 01UU 0000 0000 */
249 #define MCA_ERRCODE_INT_DETECT 0xfc00
250 #define MCA_ERRCODE_INT_UU_SH 8 /* Internal Error Type */
251 #define MCA_ERRCODE_INT_UU_MASK (0x3 << MCA_ERRCODE_INT_UU_SH)
252
253 #define MCA_BANK_LS 0 /* Load-store, including DC */
254 #define MCA_BANK_IF 1 /* Instruction Fetch, including IC */
255 #define MCA_BANK_CU 2 /* Combined Unit, including L2 */
256 /* bank 3 reserved */
257 #define MCA_BANK_NB 4 /* Northbridge, including IO link */
258 #define MCA_BANK_EX 5 /* Execution Unit */
259 #define MCA_BANK_FP 6 /* Floating Point */
260
261 enum mca_err_code_types {
262 MCA_ERRTYPE_UNKNOWN,
263 MCA_ERRTYPE_TLB,
264 MCA_ERRTYPE_MEM,
265 MCA_ERRTYPE_BUS,
266 MCA_ERRTYPE_INT
267 };
268
269 static inline enum mca_err_code_types mca_err_type(msr_t reg)
270 {
271 uint16_t error = mca_err_code(reg);
272 if (error & MCA_ERRCODE_BUS_DETECT) /* this order must be maintained */
273 return MCA_ERRTYPE_BUS;
274 if (error & MCA_ERRCODE_INT_DETECT)
275 return MCA_ERRTYPE_INT;
276 if (error & MCA_ERRCODE_MEM_DETECT)
277 return MCA_ERRTYPE_MEM;
278 if (error & MCA_ERRCODE_TLB_DETECT)
279 return MCA_ERRTYPE_TLB;
280 return MCA_ERRTYPE_UNKNOWN;
281 }
282
283 /**
284 * Helper for reading a MSR
285 *
286 * @param[in] reg The MSR.
287 */
288 static inline uint64_t msr_read(unsigned int reg)
289 {
290 msr_t msr = rdmsr(reg);
291 return msr.raw;
292 }
293
294 /**
295 * Helper for writing a MSR
296 *
297 * @param[in] reg The MSR.
298 * @param[in] value The value to be written to the MSR.
299 */
300 static inline void msr_write(unsigned int reg, uint64_t value)
301 {
302 msr_t msr = { .raw = value };
303 wrmsr(reg, msr);
304 }
305
306 /**
307 * Helper for (un)setting MSR bitmasks
308 *
309 * @param[in] reg The MSR.
310 * @param[in] unset Bitmask with ones to the bits to unset from the MSR.
311 * @param[in] set Bitmask with ones to the bits to set from the MSR.
312 */
313 static inline void msr_unset_and_set(unsigned int reg, uint64_t unset, uint64_t set)
314 {
315 msr_t msr;
316
317 msr = rdmsr(reg);
318 msr.raw &= ~unset;
319 msr.raw |= set;
320 wrmsr(reg, msr);
321 }
322
323 /**
324 * Helper for setting MSR bitmasks
325 *
326 * @param[in] reg The MSR.
327 * @param[in] set Bitmask with ones to the bits to set from the MSR.
328 */
329 static inline void msr_set(unsigned int reg, uint64_t set)
330 {
331 msr_unset_and_set(reg, 0, set);
332 }
333
334 /**
335 * Helper for unsetting MSR bitmasks
336 *
337 * @param[in] reg The MSR.
338 * @param[in] unset Bitmask with ones to the bits to unset from the MSR.
339 */
340 static inline void msr_unset(unsigned int reg, uint64_t unset)
341 {
342 msr_unset_and_set(reg, unset, 0);
343 }
344
345 #endif /* __ASSEMBLER__ */
346 #endif /* CPU_X86_MSR_H */
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