src/mainboard/amd/bilby/port_descriptors.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <soc/platform_descriptors.h>
   4 #include <types.h>
   5 #include "mainboard.h"
   6
   7 static const fsp_dxio_descriptor pco_dxio_descriptors[] = {
   8         { /* MXM - Entry 0 */
   9                 .port_present = true,
  10                 .engine_type = PCIE_ENGINE,
  11                 .start_logical_lane = 15,
  12                 .end_logical_lane = 8,
  13                 .device_number = 1,
  14                 .function_number = 1,
  15                 .link_aspm = ASPM_L1,
  16                 .link_aspm_L1_1 = true,
  17                 .link_aspm_L1_2 = true,
  18                 .turn_off_unused_lanes = true,
  19                 .clk_req = CLK_REQ3
  20         },
  21         { /* DEVICE_ID_DT - Entry 1 */
  22                 .port_present = true,
  23                 .engine_type = PCIE_ENGINE,
  24                 .start_logical_lane = 4,
  25                 .end_logical_lane = 7,
  26                 .device_number = 1,
  27                 .function_number = 2,
  28                 .link_aspm = ASPM_L1,
  29                 .link_aspm_L1_1 = true,
  30                 .link_aspm_L1_2 = true,
  31                 .turn_off_unused_lanes = true,
  32                 .clk_req = CLK_REQ4
  33         },
  34         { /* PCIE M.2 x2 - Entry 2 */
  35                 .port_present = true,
  36                 .engine_type = PCIE_ENGINE,
  37                 .start_logical_lane = 0,
  38                 .end_logical_lane = 3,
  39                 .device_number = 1,
  40                 .function_number = 5,
  41                 .link_aspm = ASPM_L1,
  42                 .link_aspm_L1_1 = true,
  43                 .link_aspm_L1_2 = true,
  44                 .turn_off_unused_lanes = true,
  45                 .clk_req = CLK_REQ2
  46         },
  47 };
  48
  49 static const fsp_ddi_descriptor pco_ddi_descriptors[] = {
  50         { /* DDI0 - DP */
  51                 .connector_type = CONFIG_DDI0_CONNECTOR_TYPE,
  52                 .aux_index = AUX1,
  53                 .hdp_index = HDP1
  54         },
  55         { /* DDI1 - DP */
  56                 .connector_type = CONFIG_DDI1_CONNECTOR_TYPE,
  57                 .aux_index = AUX2,
  58                 .hdp_index = HDP2
  59         },
  60         { /* DDI2 - DP */
  61                 .connector_type = DP,
  62                 .aux_index = AUX3,
  63                 .hdp_index = HDP3,
  64         },
  65         { /* DDI3 - DP */
  66                 .connector_type = DP,
  67                 .aux_index = AUX4,
  68                 .hdp_index = HDP4,
  69         }
  70 };
  71
  72 int get_ddi_port_conn_type(uint8_t port_num)
  73 {
  74         return pco_ddi_descriptors[port_num].connector_type;
  75 }
  76
  77 void mainboard_get_dxio_ddi_descriptors(
  78                 const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
  79                 const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
  80 {
  81         *dxio_descs = pco_dxio_descriptors;
  82         *dxio_num = ARRAY_SIZE(pco_dxio_descriptors);
  83         *ddi_descs = pco_ddi_descriptors;
  84         *ddi_num = ARRAY_SIZE(pco_ddi_descriptors);
  85 }