src/mainboard/amd/birman/devicetree_phoenix_opensil.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 # TODO: Update for birman
   4
   5 chip soc/amd/phoenix
   6         register "common_config.espi_config" = "{
   7                 .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
   8                 .generic_io_range[0] = {
   9                         .base = 0x3f8,
  10                         .size = 8,
  11                 },
  12                 .generic_io_range[1] = {
  13                         .base = 0x600,
  14                         .size = 256,
  15                 },
  16                 .io_mode = ESPI_IO_MODE_QUAD,
  17                 .op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
  18                 .crc_check_enable = 1,
  19                 .alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
  20                 .periph_ch_en = 1,
  21                 .vw_ch_en = 1,
  22                 .oob_ch_en = 1,
  23                 .flash_ch_en = 0,
  24         }"
  25
  26         register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
  27                                         GPIO_I2C2_SCL | GPIO_I2C3_SCL"
  28
  29         register "i2c[0].early_init" = "1"
  30         register "i2c[1].early_init" = "1"
  31         register "i2c[2].early_init" = "1"
  32         register "i2c[3].early_init" = "1"
  33
  34         # I2C Pad Control RX Select Configuration
  35         register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
  36         register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
  37         register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V"
  38         register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V"
  39
  40         register "s0ix_enable" = "true"
  41
  42         register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
  43
  44         register "usb_phy_custom" = "true"
  45         register "usb_phy" = "{
  46                 .Usb2PhyPort[0] = {
  47                         .compdistune = 0x1,
  48                         .pllbtune = 0x1,
  49                         .pllitune = 0x0,
  50                         .pllptune = 0xc,
  51                         .sqrxtune = 0x2,
  52                         .txfslstune = 0x1,
  53                         .txpreempamptune = 0x3,
  54                         .txpreemppulsetune = 0x0,
  55                         .txrisetune = 0x1,
  56                         .txvreftune = 0x3,
  57                         .txhsxvtune = 0x3,
  58                         .txrestune = 0x2,
  59                 },
  60                 .Usb2PhyPort[1] = {
  61                         .compdistune = 0x1,
  62                         .pllbtune = 0x1,
  63                         .pllitune = 0x0,
  64                         .pllptune = 0xc,
  65                         .sqrxtune = 0x2,
  66                         .txfslstune = 0x1,
  67                         .txpreempamptune = 0x3,
  68                         .txpreemppulsetune = 0x0,
  69                         .txrisetune = 0x1,
  70                         .txvreftune = 0x3,
  71                         .txhsxvtune = 0x3,
  72                         .txrestune = 0x2,
  73                 },
  74                 .Usb2PhyPort[2] = {
  75                         .compdistune = 0x1,
  76                         .pllbtune = 0x1,
  77                         .pllitune = 0x0,
  78                         .pllptune = 0xc,
  79                         .sqrxtune = 0x2,
  80                         .txfslstune = 0x1,
  81                         .txpreempamptune = 0x3,
  82                         .txpreemppulsetune = 0x0,
  83                         .txrisetune = 0x1,
  84                         .txvreftune = 0x3,
  85                         .txhsxvtune = 0x3,
  86                         .txrestune = 0x2,
  87                 },
  88                 .Usb2PhyPort[3] = {
  89                         .compdistune = 0x1,
  90                         .pllbtune = 0x1,
  91                         .pllitune = 0x0,
  92                         .pllptune = 0xc,
  93                         .sqrxtune = 0x2,
  94                         .txfslstune = 0x1,
  95                         .txpreempamptune = 0x3,
  96                         .txpreemppulsetune = 0x0,
  97                         .txrisetune = 0x1,
  98                         .txvreftune = 0x3,
  99                         .txhsxvtune = 0x3,
 100                         .txrestune = 0x2,
 101                 },
 102                 .Usb2PhyPort[4] = {
 103                         .compdistune = 0x1,
 104                         .pllbtune = 0x1,
 105                         .pllitune = 0x0,
 106                         .pllptune = 0xc,
 107                         .sqrxtune = 0x2,
 108                         .txfslstune = 0x1,
 109                         .txpreempamptune = 0x3,
 110                         .txpreemppulsetune = 0x0,
 111                         .txrisetune = 0x1,
 112                         .txvreftune = 0x3,
 113                         .txhsxvtune = 0x3,
 114                         .txrestune = 0x2,
 115                 },
 116                 .Usb2PhyPort[5] = {
 117                         .compdistune = 0x1,
 118                         .pllbtune = 0x1,
 119                         .pllitune = 0x0,
 120                         .pllptune = 0xc,
 121                         .sqrxtune = 0x2,
 122                         .txfslstune = 0x1,
 123                         .txpreempamptune = 0x3,
 124                         .txpreemppulsetune = 0x0,
 125                         .txrisetune = 0x1,
 126                         .txvreftune = 0x3,
 127                         .txhsxvtune = 0x3,
 128                         .txrestune = 0x2,
 129                 },
 130                 .Usb2PhyPort[6] = {
 131                         .compdistune = 0x3,
 132                         .pllbtune = 0x1,
 133                         .pllitune = 0x0,
 134                         .pllptune = 0xc,
 135                         .sqrxtune = 0x2,
 136                         .txfslstune = 0x1,
 137                         .txpreempamptune = 0x3,
 138                         .txpreemppulsetune = 0x0,
 139                         .txrisetune = 0x1,
 140                         .txvreftune = 0x6,
 141                         .txhsxvtune = 0x3,
 142                         .txrestune = 0x2,
 143                 },
 144                 .Usb2PhyPort[7] = {
 145                         .compdistune = 0x3,
 146                         .pllbtune = 0x1,
 147                         .pllitune = 0x0,
 148                         .pllptune = 0xc,
 149                         .sqrxtune = 0x2,
 150                         .txfslstune = 0x1,
 151                         .txpreempamptune = 0x3,
 152                         .txpreemppulsetune = 0x0,
 153                         .txrisetune = 0x1,
 154                         .txvreftune = 0x6,
 155                         .txhsxvtune = 0x3,
 156                         .txrestune = 0x2,
 157                 },
 158                 .Usb3PhyPort[0] = {
 159                         .tx_term_ctrl = 0x2,
 160                         .rx_term_ctrl = 0x2,
 161                         .tx_vboost_lvl_en = 0x0,
 162                         .tx_vboost_lvl = 0x5,
 163                 },
 164                 .Usb3PhyPort[1] = {
 165                         .tx_term_ctrl = 0x2,
 166                         .rx_term_ctrl = 0x2,
 167                         .tx_vboost_lvl_en = 0x0,
 168                         .tx_vboost_lvl = 0x5,
 169                 },
 170                 .Usb3PhyPort[2] = {
 171                         .tx_term_ctrl = 0x2,
 172                         .rx_term_ctrl = 0x2,
 173                         .tx_vboost_lvl_en = 0x0,
 174                         .tx_vboost_lvl = 0x5,
 175                 },
 176                 .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
 177                 .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
 178                 .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
 179                 .BatteryChargerEnable = 0,
 180                 .PhyP3CpmP4Support = 0,
 181         }"
 182
 183         register "ddi[0]" = "{
 184                 .connector_type = DDI_EDP,
 185                 .aux_index = 0,
 186                 .hdp_index = 0,
 187         }"
 188         register "ddi[1]" = "{
 189                 .connector_type = DDI_HDMI,
 190                 .aux_index = 1,
 191                 .hdp_index = 1,
 192         }"
 193         register "ddi[2]" = "{
 194                 .connector_type = DDI_DP_W_TYPEC,
 195                 .aux_index = 2,
 196                 .hdp_index = 2,
 197         }"
 198         register "ddi[3]" = "{
 199                 .connector_type = DDI_DP_W_TYPEC,
 200                 .aux_index = 3,
 201                 .hdp_index = 3,
 202         }"
 203         register "ddi[4]" = "{
 204                 .connector_type = DDI_DP_W_TYPEC,
 205                 .aux_index = 4,
 206                 .hdp_index = 4,
 207         }"
 208
 209         device domain 0 on
 210                 device ref iommu on end
 211                 chip drivers/amd/opensil/mpio
 212                         register "type" = "IFTYPE_PCIE"
 213                         register "start_lane" = "0"
 214                         register "end_lane" = "7"
 215                         register "aspm" = "ASPM_L1"
 216                         register "clk_req" = "CLK_REQ0"
 217                         # register "gpio_group" is currently not used
 218                         device ref gpp_bridge_1_1 on end # MXM
 219                 end
 220                 chip drivers/amd/opensil/mpio
 221                         register "type" = "IFTYPE_PCIE"
 222                         register "start_lane" = "8"
 223                         register "end_lane" = "11"
 224                         register "aspm" = "ASPM_L1"
 225                         register "clk_req" = "CLK_REQ1"
 226                         device ref gpp_bridge_1_2 on # NVMe SSD1
 227                                 # Required so the NVMe gets placed into D3 when entering S0i3.
 228                                 chip drivers/pcie/rtd3/device
 229                                         register "name" = ""NVME""
 230                                         device pci 00.0 on end
 231                                 end
 232                         end
 233                 end
 234                 chip drivers/amd/opensil/mpio
 235                         register "type" = "IFTYPE_PCIE"
 236                         register "start_lane" = "12"
 237                         register "end_lane" = "12"
 238                         register "aspm" = "ASPM_DISABLED"
 239                         register "clk_req" = "CLK_REQ6"
 240                         device ref gpp_bridge_1_3 on end # GBE
 241                 end
 242                 chip drivers/amd/opensil/mpio
 243                         register "type" = "IFTYPE_PCIE"
 244                         register "start_lane" = "13"
 245                         register "end_lane" = "13"
 246                         register "aspm" = "ASPM_DISABLED"
 247                         register "clk_req" = "CLK_REQ5"
 248                         device ref gpp_bridge_2_1 on end # SD
 249                 end
 250                 chip drivers/amd/opensil/mpio
 251                         register "type" = "IFTYPE_PCIE"
 252                         register "start_lane" = "14"
 253                         register "end_lane" = "14"
 254                         register "aspm" = "ASPM_DISABLED"
 255                         register "clk_req" = "CLK_REQ4"
 256                         device ref gpp_bridge_2_2 on end # WWAN
 257                 end
 258                 chip drivers/amd/opensil/mpio
 259                         register "type" = "IFTYPE_PCIE"
 260                         register "start_lane" = "15"
 261                         register "end_lane" = "15"
 262                         register "aspm" = "ASPM_DISABLED"
 263                         register "clk_req" = "CLK_REQ3"
 264                         device ref gpp_bridge_2_3 on end # WIFI
 265                 end
 266                 chip drivers/amd/opensil/mpio
 267                         register "type" = "IFTYPE_PCIE"
 268                         register "start_lane" = "16"
 269                         register "end_lane" = "19"
 270                         register "aspm" = "ASPM_DISABLED"
 271                         register "clk_req" = "CLK_REQ2"
 272                         device ref gpp_bridge_2_4 on # NVMe SSD0
 273                                 # Required so the NVMe gets placed into D3 when entering S0i3.
 274                                 chip drivers/pcie/rtd3/device
 275                                         register "name" = ""NVME""
 276                                         device pci 00.0 on end
 277                                 end
 278                         end
 279                 end
 280                 device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 281                         device ref gfx on end # Internal GPU (GFX)
 282                         device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
 283                         device ref crypto on end # Crypto Coprocessor
 284                         device ref xhci_0 on # USB 3.1 (USB0)
 285                                 chip drivers/usb/acpi
 286                                         device ref xhci_0_root_hub on
 287                                                 chip drivers/usb/acpi
 288                                                         device ref usb3_port2 on end
 289                                                 end
 290                                                 chip drivers/usb/acpi
 291                                                         device ref usb3_port3 on end
 292                                                 end
 293                                                 chip drivers/usb/acpi
 294                                                         device ref usb2_port2 on end
 295                                                 end
 296                                                 chip drivers/usb/acpi
 297                                                         device ref usb2_port3 on end
 298                                                 end
 299                                                 chip drivers/usb/acpi
 300                                                         device ref usb2_port4 on end
 301                                                 end
 302                                                 chip drivers/usb/acpi
 303                                                         device ref usb2_port5 on end
 304                                                 end
 305                                                 chip drivers/usb/acpi
 306                                                         device ref usb2_port6 on end
 307                                                 end
 308                                         end
 309                                 end
 310                         end
 311                         device ref xhci_1 on # USB 3.1 (USB1)
 312                                 chip drivers/usb/acpi
 313                                         device ref xhci_1_root_hub on
 314                                                 chip drivers/usb/acpi
 315                                                         device ref usb3_port7 on end
 316                                                 end
 317                                                 chip drivers/usb/acpi
 318                                                         device ref usb2_port7 on end
 319                                                 end
 320                                         end
 321                                 end
 322                         end
 323                         device ref acp on end # Audio Processor (ACP)
 324                 end
 325                 device ref gpp_bridge_c on  # Internal GPP Bridge 2 to Bus C
 326                         device ref usb4_xhci_0 on
 327                                 chip drivers/usb/acpi
 328                                         device ref usb4_xhci_0_root_hub on
 329                                                 chip drivers/usb/acpi
 330                                                         device ref usb3_port0 on end
 331                                                 end
 332                                                 chip drivers/usb/acpi
 333                                                         device ref usb2_port0 on end
 334                                                 end
 335                                         end
 336                                 end
 337                         end
 338                         device ref usb4_xhci_1 on
 339                                 chip drivers/usb/acpi
 340                                         device ref usb4_xhci_1_root_hub on
 341                                                 chip drivers/usb/acpi
 342                                                         device ref usb3_port1 on end
 343                                                 end
 344                                                 chip drivers/usb/acpi
 345                                                         device ref usb2_port1 on end
 346                                                 end
 347                                         end
 348                                 end
 349                         end
 350                 end
 351         end
 352
 353         device ref i2c_0 on end
 354         device ref i2c_1 on end
 355         device ref i2c_2 on end
 356         device ref i2c_3 on end
 357         device ref uart_0 on end # UART0
 358
 359 end