src/mainboard/amd/gardenia/dsdt.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #define MAINBOARD_HAS_SPEAKER 1
   4
   5 /* DefinitionBlock Statement */
   6 #include <acpi/acpi.h>
   7 DefinitionBlock (
   8         "dsdt.aml",
   9         "DSDT",
  10         ACPI_DSDT_REV_2,
  11         OEM_ID,
  12         ACPI_TABLE_CREATOR,
  13         0x00010001      /* OEM Revision */
  14         )
  15 {       /* Start of ASL file */
  16         #include <acpi/dsdt_top.asl>
  17         #include <globalnvs.asl>
  18
  19         /* Describe the USB Overcurrent pins */
  20         #include "acpi/usb_oc.asl"
  21
  22         /* PCI IRQ mapping for the Southbridge */
  23         #include <pcie.asl>
  24
  25         /* Power state notification */
  26         #include <pnot.asl>
  27
  28         /* Contains the supported sleep states for this chipset */
  29         #include <soc/amd/common/acpi/sleepstates.asl>
  30
  31         /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
  32         #include "acpi/sleep.asl"
  33
  34         /* System Bus */
  35         Scope(\_SB) { /* Start \_SB scope */
  36                 /* global utility methods expected within the \_SB scope */
  37                 #include <arch/x86/acpi/globutil.asl>
  38
  39                 /* IRQ Routing mapping for this platform (in \_SB scope) */
  40                 #include "acpi/routing.asl"
  41
  42                 Device(PWRB) {
  43                         Name(_HID, EISAID("PNP0C0C"))
  44                         Name(_UID, 0xAA)
  45                         Name(_PRW, Package () {3, 0x04})
  46                         Name(_STA, 0x0B)
  47                 }
  48
  49                 /* Describe the SOC */
  50                 #include <soc.asl>
  51
  52         } /* End \_SB scope */
  53
  54         /* Define the General Purpose Events for the platform */
  55         #include "acpi/gpe.asl"
  56 }
  57 /* End of ASL file */