util/docker/doc.coreboot.org: Allow git to work in envs owned by root
[coreboot2.git] / src / mainboard / compulab / intense_pc / devicetree.cb
blob0c793095632b55b70f116172b6b7a64f1748adfa
1 # SPDX-License-Identifier: GPL-2.0-only
3 chip northbridge/intel/sandybridge # FIXME: check gfx
4 register "gfx" = "GMA_STATIC_DISPLAYS(0)"
5 register "gpu_dp_b_hotplug" = "4"
6 register "gpu_dp_c_hotplug" = "4"
7 register "gpu_dp_d_hotplug" = "4"
9 register "spd_addresses" = "{0x50, 0, 0x52, 0}"
11 device domain 0 on
12 device ref host_bridge on # Host bridge
13 subsystemid 0x8086 0x2010
14 end
15 device ref peg10 on # PCIe Bridge for discrete graphics
16 subsystemid 0x8086 0x2010
17 end
18 device ref peg11 on # PCIe Bridge for discrete graphics
19 subsystemid 0x8086 0x2010
20 end
21 device ref igd on # Internal graphics VGA controller
22 subsystemid 0x8086 0x2211
23 end
25 subsystemid 0x8086 0x7270 inherit
26 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
27 register "docking_supported" = "1"
28 register "gen1_dec" = "0x0000164d"
29 register "gen2_dec" = "0x000c0681"
30 register "gen3_dec" = "0x000406f1"
31 register "gen4_dec" = "0x000c06a1"
32 register "gpi7_routing" = "2"
33 register "pcie_port_coalesce" = "true"
34 register "sata_interface_speed_support" = "0x3"
35 # Intense PC SATA portmap:
36 # Port 0: internal 2.5" bay
37 # Port 1: optional FACE module
38 # Port 2: rear eSATA
39 # Port 3: rear eSATA
40 # Port 4: mSATA
41 # Port 5: optional FACE module
42 # enable ALL ports (FACE module REQUIRED for ports 1&5)
43 register "sata_port_map" = "0x3f"
44 # enable ONLY ports present on stock MintBox/Intense PC
45 #register "sata_port_map" = "0x1d"
46 register "superspeed_capable_ports" = "0x0000000f"
47 register "xhci_overcurrent_mapping" = "0x00000c03"
48 register "xhci_switchable_ports" = "0x0000000f"
49 register "spi_uvscc" = "0x2005"
50 register "spi_lvscc" = "0x2005"
51 register "usb_port_config" = "{
52 { 1, 1, 0 },
53 { 1, 1, 0 },
54 { 1, 1, 1 },
55 { 1, 1, 1 },
56 { 1, 0, 2 },
57 { 1, 0, 2 },
58 { 1, 0, 3 },
59 { 1, 0, 3 },
60 { 1, 1, 4 },
61 { 1, 1, 4 },
62 { 1, 0, 5 },
63 { 1, 0, 5 },
64 { 1, 0, 6 },
65 { 1, 0, 6 }
68 device ref xhci on end # USB 3.0 Controller
69 device ref mei1 off end # Management Engine Interface 1
70 device ref mei2 off end # Management Engine Interface 2
71 device ref me_ide_r off end # Management Engine IDE-R
72 device ref me_kt off end # Management Engine KT
73 device ref gbe on end # Intel Gigabit Ethernet
74 device ref ehci2 on end # USB2 EHCI #2
75 device ref hda on end # High Definition Audio
76 device ref pcie_rp1 on end # PCIe Port #1
77 device ref pcie_rp2 on end # PCIe Port #2
78 device ref pcie_rp3 on end # PCIe Port #3
79 device ref pcie_rp4 off end # PCIe Port #4
80 device ref pcie_rp5 on end # PCIe Port #5
81 device ref pcie_rp6 off end # PCIe Port #6
82 device ref pcie_rp7 off end # PCIe Port #7
83 device ref pcie_rp8 off end # PCIe Port #8
84 device ref ehci1 on end # USB2 EHCI #1
85 device ref pci_bridge off end # PCI bridge
86 device ref lpc on end # LPC bridge
87 device ref sata1 on end # SATA Controller 1
88 device ref smbus on end # SMBus
89 device ref sata2 off end # SATA Controller 2
90 device ref thermal on end # Thermal
91 end
92 end
93 end