src/mainboard/emulation/spike-riscv/memlayout.ld

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <memlayout.h>
   4
   5 #include <arch/header.ld>
   6
   7 #define START 0x80000000
   8
   9 SECTIONS
  10 {
  11         DRAM_START(START)
  12         BOOTBLOCK(START, 64K)
  13         STACK(START + 8M, 4K)
  14         FMAP_CACHE(START + 8M + 4K, 2K)
  15         CBFS_MCACHE(START + 8M + 6K, 8K)
  16         /* hole at (START + 8M + 14K, 50K) */
  17         ROMSTAGE(START + 8M + 64K, 128K)
  18         PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
  19         RAMSTAGE(START + 8M + 200K, 2M)
  20 }