soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / mainboard / getac / p470 / dsdt.asl
blob107d549a9e998bd6d68248417d182316a2b36f5b
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #define ENABLE_TPM
5 #include <acpi/acpi.h>
6 DefinitionBlock(
7         "dsdt.aml",
8         "DSDT",
9         ACPI_DSDT_REV_2,
10         OEM_ID,
11         ACPI_TABLE_CREATOR,
12         0x20090419      // OEM revision
15         #include <acpi/dsdt_top.asl>
16         #include <southbridge/intel/common/acpi/platform.asl>
18         #include "acpi/platform.asl"
20         // global NVS and variables
21         #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
23         // General Purpose Events
24         #include "acpi/gpe.asl"
26         // mainboard specific devices
27         #include "acpi/mainboard.asl"
29         // Thermal Zone
30         #include "acpi/thermal.asl"
32         #include <cpu/intel/speedstep/acpi/cpu.asl>
34         Scope (\_SB) {
35                 Device (PCI0)
36                 {
37                         #include <northbridge/intel/i945/acpi/i945.asl>
38                         #include <southbridge/intel/i82801gx/acpi/ich7.asl>
39                 }
40         }
42         #include <southbridge/intel/common/acpi/sleepstates.asl>