1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/device.h>
4 #include <arch/smp/mpspec.h>
5 #include <arch/ioapic.h>
7 static void *smp_write_config_table(void *v
)
9 struct mp_config_table
*mc
;
12 mc
= (void *)(((char *)v
) + SMP_FLOATING_TABLE_LEN
);
16 smp_write_processors(mc
);
18 mptable_write_buses(mc
, nullptr, &isa_bus
);
20 /* I/O APICs: APIC ID Version State Address */
21 u8 ioapic_id
= smp_write_ioapic_from_hw(mc
, IO_APIC_ADDR
);
23 /* Legacy Interrupts */
24 mptable_add_isa_interrupts(mc
, isa_bus
, ioapic_id
, 0);
26 /* Builtin devices on Bus 0 */
27 smp_write_pci_intsrc(mc
, mp_INT
, 0x0, 0x02, 0, ioapic_id
, 0x10);
28 smp_write_pci_intsrc(mc
, mp_INT
, 0x0, 0x1f, 1, ioapic_id
, 0x13);
29 smp_write_pci_intsrc(mc
, mp_INT
, 0x0, 0x1d, 0, ioapic_id
, 0x17);
30 smp_write_pci_intsrc(mc
, mp_INT
, 0x0, 0x1d, 1, ioapic_id
, 0x13);
31 smp_write_pci_intsrc(mc
, mp_INT
, 0x0, 0x1d, 2, ioapic_id
, 0x12);
32 smp_write_pci_intsrc(mc
, mp_INT
, 0x0, 0x1d, 3, ioapic_id
, 0x10);
33 smp_write_pci_intsrc(mc
, mp_INT
, 0x0, 0x1b, 0, ioapic_id
, 0x10);
34 smp_write_pci_intsrc(mc
, mp_INT
, 0x0, 0x1c, 0, ioapic_id
, 0x10);
35 smp_write_pci_intsrc(mc
, mp_INT
, 0x0, 0x1c, 1, ioapic_id
, 0x11);
38 smp_write_pci_intsrc(mc
, mp_INT
, 0x4, 0x00, 0, ioapic_id
, 0x10);
40 // riser slot top 5:8.0
41 smp_write_pci_intsrc(mc
, mp_INT
, 0x5, 0x08, 0, ioapic_id
, 0x14);
42 // riser slot middle 5:9.0
43 smp_write_pci_intsrc(mc
, mp_INT
, 0x5, 0x09, 0, ioapic_id
, 0x15);
44 // riser slot bottom 5:a.0
45 smp_write_pci_intsrc(mc
, mp_INT
, 0x5, 0x0a, 0, ioapic_id
, 0x16);
47 /* Onboard Ethernet */
48 smp_write_pci_intsrc(mc
, mp_INT
, 0x1, 0x00, 0, ioapic_id
, 0x10);
50 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
51 mptable_lintsrc(mc
, isa_bus
);
53 /* Compute the checksums */
54 return mptable_finalize(mc
);
57 unsigned long write_smp_table(unsigned long addr
)
60 v
= smp_write_floating_table(addr
, 0);
61 return (unsigned long)smp_write_config_table(v
);