src/mainboard/google/auron/variants/auron_yuna/overridetree.cb

   1 chip soc/intel/broadwell
   2
   3         register "panel_cfg" = "{
   4                 .up_delay_ms            =  40,
   5                 .down_delay_ms          =  15,
   6                 .cycle_delay_ms         = 400,
   7                 .backlight_on_delay_ms  = 210,
   8                 .backlight_off_delay_ms = 210,
   9                 .backlight_pwm_hz       = 200,
  10         }"
  11
  12         device domain 0 on
  13                 chip soc/intel/broadwell/pch
  14                         # DTLE DATA / EDGE values
  15                         register "sata_port0_gen3_dtle" = "0x7"
  16                         register "sata_port1_gen3_dtle" = "0x5"
  17
  18                         device pci 1f.2 on  end # SATA Controller
  19                 end
  20         end
  21 end