src/mainboard/google/brya/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpigen.h>
   4 #include <baseboard/gpio.h>
   5 #include <baseboard/variants.h>
   6 #include <device/device.h>
   7 #include <drivers/tpm/cr50.h>
   8 #include <drivers/wwan/fm/chip.h>
   9 #include <ec/ec.h>
  10 #include <fw_config.h>
  11 #include <security/tpm/tss.h>
  12 #include <soc/gpio.h>
  13 #include <soc/ramstage.h>
  14 #include <static.h>
  15 #include <stdio.h>
  16
  17 WEAK_DEV_PTR(rp6_wwan);
  18 WEAK_DEV_PTR(dgpu);
  19
  20 static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
  21 {
  22         struct smbios_type11 *t;
  23         char buffer[64];
  24
  25         t = (struct smbios_type11 *)arg;
  26
  27         snprintf(buffer, sizeof(buffer), "%s-%s", config->field_name, config->option_name);
  28         t->count = smbios_add_string(t->eos, buffer);
  29 }
  30
  31 static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t)
  32 {
  33         fw_config_for_each_found(add_fw_config_oem_string, t);
  34 }
  35
  36 void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config)
  37 {
  38         tpm_result_t rc;
  39
  40         rc = tlcl_lib_init();
  41         if (rc != TPM_SUCCESS) {
  42                 printk(BIOS_ERR, "tlcl_lib_init() failed: %#x\n", rc);
  43                 return;
  44         }
  45
  46         if (cr50_is_long_interrupt_pulse_enabled()) {
  47                 printk(BIOS_INFO, "Enabling GPIO PM b/c CR50 has long IRQ pulse support\n");
  48                 config->gpio_override_pm = 0;
  49         } else {
  50                 printk(BIOS_INFO, "Disabling GPIO PM b/c CR50 does not have long IRQ pulse "
  51                        "support\n");
  52                 config->gpio_override_pm = 1;
  53                 config->gpio_pm[COMM_0] = 0;
  54                 config->gpio_pm[COMM_1] = 0;
  55                 config->gpio_pm[COMM_2] = 0;
  56                 config->gpio_pm[COMM_3] = 0;
  57                 config->gpio_pm[COMM_4] = 0;
  58                 config->gpio_pm[COMM_5] = 0;
  59         }
  60
  61         variant_update_soc_chip_config(config);
  62 }
  63
  64 void __weak variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
  65 {
  66         /* default implementation does nothing */
  67 }
  68
  69 void __weak variant_init(void)
  70 {
  71         /* default implementation does nothing */
  72 }
  73
  74 void __weak fw_config_gpio_padbased_override(struct pad_config *padbased_table)
  75 {
  76         /* default implementation does nothing */
  77 }
  78
  79 void __weak variant_configure_pads(void)
  80 {
  81         const struct pad_config *base_pads;
  82         const struct pad_config *override_pads;
  83         size_t base_num, override_num;
  84
  85         base_pads = variant_gpio_table(&base_num);
  86         override_pads = variant_gpio_override_table(&override_num);
  87         gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
  88 }
  89
  90 static void mainboard_init(void *chip_info)
  91 {
  92         variant_configure_pads();
  93         variant_init();
  94         variant_devtree_update();
  95 }
  96
  97 void __weak variant_devtree_update(void)
  98 {
  99         /* Override dev tree settings per board */
 100 }
 101
 102 static void mainboard_dev_init(struct device *dev)
 103 {
 104         mainboard_ec_init();
 105 }
 106
 107 static void mainboard_generate_wwan_shutdown(const struct device *dev)
 108 {
 109         const struct drivers_wwan_fm_config *config = config_of(dev);
 110         const struct device *parent = dev->upstream->dev;
 111
 112         if (!config)
 113                 return;
 114         if (config->rtd3dev) {
 115                 acpigen_write_store();
 116                 acpigen_emit_namestring(acpi_device_path_join(parent, "RTD3._STA"));
 117                 acpigen_emit_byte(LOCAL0_OP);
 118                 acpigen_write_if_lequal_op_int(LOCAL0_OP, ONE_OP);
 119                 {
 120                         acpigen_emit_namestring(acpi_device_path_join(dev, "DPTS"));
 121                         acpigen_emit_byte(ARG0_OP);
 122                 }
 123                 acpigen_write_if_end();
 124         }
 125 }
 126
 127 static void mainboard_generate_dgpu_shutdown(const struct device *dev)
 128 {
 129         /* Call `_OFF` from the Power Resource associated with the dGPU's PEG port. */
 130         const struct device *parent = dev->upstream->dev;
 131
 132         if (parent)
 133                 acpigen_emit_namestring(acpi_device_path_join(parent, "PGPR._OFF"));
 134 }
 135
 136 static void mainboard_generate_mpts(void)
 137 {
 138         const struct device *wwan = DEV_PTR(rp6_wwan);
 139         const struct device *dgpu = DEV_PTR(dgpu);
 140
 141         /*
 142          * If HAVE_WWAN_POWER_SEQUENCE is selected, MPTS will be added to the
 143          * DSDT via wwan_power.asl. We can't add MPTS to the SSDT as well,
 144          * since the duplicate definition will result in a kernel error.
 145          *
 146          * This special case can be removed in the future if the power-off
 147          * sequences for all WWAN devices used on brya are moved to the SSDT.
 148          */
 149         if (CONFIG(HAVE_WWAN_POWER_SEQUENCE)) {
 150                 if (wwan || dgpu)
 151                         printk(BIOS_ERR, "Skip adding duplicate MPTS entry to SSDT\n");
 152                 return;
 153         }
 154
 155         acpigen_write_scope("\\_SB");
 156         acpigen_write_method_serialized("MPTS", 1);
 157         if (wwan)
 158                 mainboard_generate_wwan_shutdown(wwan);
 159         if (dgpu)
 160                 mainboard_generate_dgpu_shutdown(dgpu);
 161
 162         acpigen_write_method_end(); /* Method */
 163         acpigen_write_scope_end(); /* Scope */
 164 }
 165
 166 static void mainboard_generate_s0ix_hook(void)
 167 {
 168         acpigen_write_if_lequal_op_int(ARG0_OP, 1);
 169         {
 170                 if (CONFIG(HAVE_SLP_S0_GATE))
 171                         acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE);
 172                 variant_generate_s0ix_hook(S0IX_ENTRY);
 173         }
 174         acpigen_write_else();
 175         {
 176                 if (CONFIG(HAVE_SLP_S0_GATE))
 177                         acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE);
 178                 variant_generate_s0ix_hook(S0IX_EXIT);
 179         }
 180         acpigen_write_if_end();
 181 }
 182
 183 static void mainboard_fill_ssdt(const struct device *dev)
 184 {
 185         mainboard_generate_mpts();
 186
 187         /* for variant to fill additional SSDT */
 188         variant_fill_ssdt(dev);
 189
 190         acpigen_write_scope("\\_SB");
 191         acpigen_write_method_serialized("MS0X", 1);
 192         mainboard_generate_s0ix_hook();
 193         acpigen_write_method_end(); /* Method */
 194         acpigen_write_scope_end(); /* Scope */
 195 }
 196
 197 void __weak variant_fill_ssdt(const struct device *dev)
 198 {
 199         /* Add board-specific SSDT entries */
 200 }
 201
 202 void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
 203 {
 204         /* Add board-specific MS0X entries */
 205         /*
 206            if (s0ix_entry == S0IX_ENTRY) {
 207                 implement variant operations here
 208            }
 209            if (s0ix_entry == S0IX_EXIT) {
 210                 implement variant operations here
 211            }
 212          */
 213 }
 214
 215 static void mainboard_enable(struct device *dev)
 216 {
 217         dev->ops->init = mainboard_dev_init;
 218         dev->ops->get_smbios_strings = mainboard_smbios_strings;
 219         dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 220 }
 221
 222
 223 void __weak variant_finalize(void)
 224 {
 225 }
 226
 227 static void mainboard_final(void *chip_info)
 228 {
 229         variant_finalize();
 230 }
 231
 232 struct chip_operations mainboard_ops = {
 233         .init = mainboard_init,
 234         .enable_dev = mainboard_enable,
 235         .final = mainboard_final,
 236 };