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mb/google/fatcat: config GPP_F23 as ISH gpio pin
[coreboot2.git] / src / mainboard / google / brya / variants / craaskov / overridetree.cb
blob476e642660e5465418cfab074360ec45e403b55d
1 fw_config
2 field THERMAL_SOLUTION 0 0
3 option THERMAL_SOLUTION_6W 0
4 option THERMAL_SOLUTION_15W 1
5 end
6 end
7
8 chip soc/intel/alderlake
9 register "sagv" = "SaGv_Enabled"
10
11 # EMMC Tx CMD Delay
12 # Refer to EDS-Vol2-42.3.7.
13 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
14 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
15 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
16
17 # EMMC TX DATA Delay 1
18 # Refer to EDS-Vol2-42.3.8.
19 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
20 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
21 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
22
23 # EMMC TX DATA Delay 2
24 # Refer to EDS-Vol2-42.3.9.
25 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
26 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
27 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
28 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
29 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
30
31 # EMMC RX CMD/DATA Delay 1
32 # Refer to EDS-Vol2-42.3.10.
33 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
34 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
35 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
36 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
37 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
38
39 # EMMC RX CMD/DATA Delay 2
40 # Refer to EDS-Vol2-42.3.12.
41 # [17:16] stands for Rx Clock before Output Buffer,
42 # 00: Rx clock after output buffer,
43 # 01: Rx clock before output buffer,
44 # 10: Automatic selection based on working mode.
45 # 11: Reserved
46 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
47 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
48 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E"
49
50 # EMMC Rx Strobe Delay
51 # Refer to EDS-Vol2-42.3.11.
52 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
53 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
54 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
55
56 # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
57 # Bit 2 - C1 has a redriver which does SBU muxing.
58 # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
59 register "tcss_aux_ori" = "1"
60
61 register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
62
63 register "serial_io_i2c_mode" = "{
64 [PchSerialIoIndexI2C0] = PchSerialIoPci,
65 [PchSerialIoIndexI2C1] = PchSerialIoPci,
66 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
67 [PchSerialIoIndexI2C3] = PchSerialIoPci,
68 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
69 [PchSerialIoIndexI2C5] = PchSerialIoPci,
70 }"
71
72 # Intel Common SoC Config
73 #+-------------------+---------------------------+
74 #| Field | Value |
75 #+-------------------+---------------------------+
76 #| I2C0 | TPM. Early init is |
77 #| | required to set up a BAR |
78 #| | for TPM communication |
79 #| I2C1 | Touchscreen |
80 #| I2C3 | Audio |
81 #| I2C5 | Trackpad |
82 #+-------------------+---------------------------+
83 register "common_soc_config" = "{
84 .i2c[0] = {
85 .early_init = 1,
86 .speed = I2C_SPEED_FAST_PLUS,
87 .speed_config[0] = {
88 .speed = I2C_SPEED_FAST_PLUS,
89 .scl_lcnt = 55,
90 .scl_hcnt = 30,
91 .sda_hold = 7,
92 }
93 },
94 .i2c[1] = {
95 .speed = I2C_SPEED_FAST,
96 .speed_config[0] = {
97 .speed = I2C_SPEED_FAST,
98 .scl_lcnt = 158,
99 .scl_hcnt = 79,
100 .sda_hold = 7,
101 }
102 },
103 .i2c[3] = {
104 .speed = I2C_SPEED_FAST,
105 .speed_config[0] = {
106 .speed = I2C_SPEED_FAST,
107 .scl_lcnt = 158,
108 .scl_hcnt = 79,
109 .sda_hold = 7,
110 }
111 },
112 .i2c[5] = {
113 .speed = I2C_SPEED_FAST,
114 .speed_config[0] = {
115 .speed = I2C_SPEED_FAST,
116 .scl_lcnt = 158,
117 .scl_hcnt = 79,
118 .sda_hold = 7,
119 }
120 },
121 }"
122
123 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2
124 register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5
125 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7
126 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
127 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
128
129 register "power_limits_config[ADL_N_041_6W_CORE]" = "{
130 .tdp_pl1_override = 20,
131 .tdp_pl2_override = 25,
132 .tdp_pl4 = 78,
133 }"
134
135 register "power_limits_config[ADL_N_081_15W_CORE]" = "{
136 .tdp_pl1_override = 20,
137 .tdp_pl2_override = 35,
138 .tdp_pl4 = 83,
139 }"
140
141 device domain 0 on
142 device ref dtt on
143 chip drivers/intel/dptf
144 ## sensor information
145 register "options.tsr[0].desc" = ""DDR""
146 register "options.tsr[1].desc" = ""charger""
147 register "options.tsr[2].desc" = ""ambient""
148
149 ## Active Policy
150 register "policies.active" = "{
151 [0] = {
152 .target = DPTF_CPU,
153 .thresholds = {
154 TEMP_PCT(95, 100),
155 TEMP_PCT(83, 64),
156 TEMP_PCT(72, 59),
157 TEMP_PCT(65, 54),
158 TEMP_PCT(52, 49),
159 TEMP_PCT(42, 43),
160 TEMP_PCT(38, 29),
161 }
162 },
163 [1] = {
164 .target = DPTF_TEMP_SENSOR_0,
165 .thresholds = {
166 TEMP_PCT(60, 100),
167 TEMP_PCT(55, 64),
168 TEMP_PCT(52, 59),
169 TEMP_PCT(50, 54),
170 TEMP_PCT(48, 49),
171 TEMP_PCT(45, 43),
172 TEMP_PCT(41, 29),
173 }
174 }
175 }"
176
177 ## Passive Policy
178 register "policies.passive" = "{
179 [0] = DPTF_PASSIVE(CPU, CPU, 85, 5000),
180 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 5000),
181 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 5000),
182 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 5000),
183 }"
184
185 ## Critical Policy
186 register "policies.critical" = "{
187 [0] = DPTF_CRITICAL(CPU, 110, SHUTDOWN),
188 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN),
189 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN),
190 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN),
191 }"
192
193 register "controls.power_limits" = "{
194 .pl1 = {
195 .min_power = 6000,
196 .max_power = 6000,
197 .time_window_min = 28 * MSECS_PER_SEC,
198 .time_window_max = 28 * MSECS_PER_SEC,
199 .granularity = 500
200 },
201 .pl2 = {
202 .min_power = 6000,
203 .max_power = 6000,
204 .time_window_min = 32 * MSECS_PER_SEC,
205 .time_window_max = 32 * MSECS_PER_SEC,
206 .granularity = 500
207 }
208 }"
209
210 ## Charger Performance Control (Control, mA)
211 register "controls.charger_perf" = "{
212 [0] = { 255, 1700 },
213 [1] = { 24, 1500 },
214 [2] = { 16, 1000 },
215 [3] = { 8, 500 }
216 }"
217
218 ## Fan Performance Control (Percent, Speed, Noise, Power)
219 register "controls.fan_perf" = "{
220 [0] = { 100, 6000, 220, 2200, },
221 [1] = { 92, 5500, 180, 1800, },
222 [2] = { 85, 5000, 145, 1450, },
223 [3] = { 70, 4400, 115, 1150, },
224 [4] = { 56, 3900, 90, 900, },
225 [5] = { 45, 3300, 55, 550, },
226 [6] = { 38, 3000, 30, 300, },
227 [7] = { 33, 2900, 15, 150, },
228 [8] = { 10, 800, 10, 100, },
229 [9] = { 0, 0, 0, 50, }
230 }"
231
232 ## Fan options
233 register "options.fan.fine_grained_control" = "1"
234 register "options.fan.step_size" = "2"
235
236 device generic 0 on
237 probe THERMAL_SOLUTION THERMAL_SOLUTION_6W
238 end
239 end
240 chip drivers/intel/dptf
241 ## sensor information
242 register "options.tsr[0].desc" = ""DDR""
243 register "options.tsr[1].desc" = ""charger""
244 register "options.tsr[2].desc" = ""ambient""
245
246 ## Active Policy
247 register "policies.active" = "{
248 [0] = {
249 .target = DPTF_CPU,
250 .thresholds = {
251 TEMP_PCT(70, 100),
252 TEMP_PCT(60, 65),
253 TEMP_PCT(42, 58),
254 TEMP_PCT(39, 53),
255 TEMP_PCT(38, 47),
256 TEMP_PCT(35, 43),
257 TEMP_PCT(31, 30),
258 }
259 },
260 [1] = {
261 .target = DPTF_TEMP_SENSOR_0,
262 .thresholds = {
263 TEMP_PCT(60, 100),
264 TEMP_PCT(55, 65),
265 TEMP_PCT(52, 58),
266 TEMP_PCT(50, 53),
267 TEMP_PCT(48, 47),
268 TEMP_PCT(45, 43),
269 TEMP_PCT(41, 30),
270 }
271 }
272 }"
273
274 ## Passive Policy
275 register "policies.passive" = "{
276 [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
277 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
278 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
279 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
280 }"
281
282 ## Critical Policy
283 register "policies.critical" = "{
284 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
285 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN),
286 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),
287 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN),
288 }"
289
290 register "controls.power_limits" = "{
291 .pl1 = {
292 .min_power = 15000,
293 .max_power = 15000,
294 .time_window_min = 28 * MSECS_PER_SEC,
295 .time_window_max = 28 * MSECS_PER_SEC,
296 .granularity = 500
297 },
298 .pl2 = {
299 .min_power = 15000,
300 .max_power = 15000,
301 .time_window_min = 32 * MSECS_PER_SEC,
302 .time_window_max = 32 * MSECS_PER_SEC,
303 .granularity = 500
304 }
305 }"
306
307 ## Charger Performance Control (Control, mA)
308 register "controls.charger_perf" = "{
309 [0] = { 255, 1700 },
310 [1] = { 24, 1500 },
311 [2] = { 16, 1000 },
312 [3] = { 8, 500 }
313 }"
314
315 ## Fan Performance Control (Percent, Speed, Noise, Power)
316 register "controls.fan_perf" = "{
317 [0] = { 100, 6000, 220, 2200, },
318 [1] = { 92, 5500, 180, 1800, },
319 [2] = { 85, 5000, 145, 1450, },
320 [3] = { 70, 4400, 115, 1150, },
321 [4] = { 56, 3900, 90, 900, },
322 [5] = { 45, 3300, 55, 550, },
323 [6] = { 38, 3000, 30, 300, },
324 [7] = { 33, 2900, 15, 150, },
325 [8] = { 10, 800, 10, 100, },
326 [9] = { 0, 0, 0, 50, }
327 }"
328
329 ## Fan options
330 register "options.fan.fine_grained_control" = "1"
331 register "options.fan.step_size" = "2"
332
333 device generic 1 on
334 probe THERMAL_SOLUTION THERMAL_SOLUTION_15W
335 end
336 end
337 end
338 device ref i2c1 on
339 chip drivers/i2c/hid
340 register "generic.hid" = ""ELAN9004""
341 register "generic.desc" = ""ELAN Touchscreen""
342 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
343 register "generic.detect" = "1"
344 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
345 register "generic.reset_delay_ms" = "20"
346 register "generic.reset_off_delay_ms" = "2"
347 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
348 register "generic.enable_delay_ms" = "6"
349 register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
350 register "generic.stop_delay_ms" = "150"
351 register "generic.stop_off_delay_ms" = "2"
352 register "generic.has_power_resource" = "1"
353 register "hid_desc_reg_offset" = "0x01"
354 device i2c 10 on end
355 end
356 end #I2C1
357 device ref i2c3 on
358 chip drivers/i2c/generic
359 register "hid" = ""10EC5650""
360 register "name" = ""RT58""
361 register "desc" = ""Realtek RT5650""
362 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
363 register "property_count" = "1"
364 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
365 register "property_list[0].name" = ""realtek,jd-mode""
366 register "property_list[0].integer" = "2"
367 device i2c 1a on end
368 end
369 end #I2C3
370 device ref i2c5 on
371 chip drivers/i2c/generic
372 register "hid" = ""ELAN0000""
373 register "desc" = ""ELAN Touchpad""
374 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
375 register "wake" = "GPE0_DW2_14"
376 register "detect" = "1"
377 device i2c 15 on end
378 end
379 chip drivers/i2c/hid
380 register "generic.hid" = ""SYNA0000""
381 register "generic.cid" = ""ACPI0C50""
382 register "generic.desc" = ""Synaptics Touchpad""
383 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
384 register "generic.wake" = "GPE0_DW2_14"
385 register "generic.detect" = "1"
386 register "hid_desc_reg_offset" = "0x20"
387 device i2c 2c on end
388 end
389 chip drivers/i2c/hid
390 register "generic.hid" = ""PIXA2303""
391 register "generic.desc" = ""PIXA Touchpad""
392 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
393 register "generic.wake" = "GPE0_DW2_14"
394 register "generic.detect" = "1"
395 register "hid_desc_reg_offset" = "0x20"
396 device i2c 0x68 on end
397 end
398 end
399 device ref pcie_rp7 off end
400 device ref emmc on end
401 device ref ish on
402 chip drivers/intel/ish
403 register "add_acpi_dma_property" = "true"
404 device generic 0 on end
405 end
406 end
407 device ref ufs on end
408 device ref cnvi_wifi on
409 chip drivers/wifi/generic
410 register "wake" = "GPE0_PME_B0"
411 register "enable_cnvi_ddr_rfim" = "true"
412 register "add_acpi_dma_property" = "true"
413 device generic 0 on end
414 end
415 end
416 device ref pch_espi on
417 chip ec/google/chromeec
418 use conn0 as mux_conn[0]
419 device pnp 0c09.0 on end
420 end
421 end
422 device ref pmc hidden
423 chip drivers/intel/pmc_mux
424 device generic 0 on
425 chip drivers/intel/pmc_mux/conn
426 use usb2_port1 as usb2_port
427 use tcss_usb3_port1 as usb3_port
428 device generic 0 alias conn0 on end
429 end
430 end
431 end
432 end
433 device ref tcss_xhci on
434 chip drivers/usb/acpi
435 device ref tcss_root_hub on
436 chip drivers/usb/acpi
437 register "desc" = ""USB3 Type-C Port C0 (MLB)""
438 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
439 register "use_custom_pld" = "true"
440 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
441 device ref tcss_usb3_port1 on end
442 end
443 end
444 end
445 end
446 device ref xhci on
447 chip drivers/usb/acpi
448 device ref xhci_root_hub on
449 chip drivers/usb/acpi
450 register "desc" = ""USB2 Type-C Port C0 (MLB)""
451 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
452 register "use_custom_pld" = "true"
453 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
454 device ref usb2_port1 on end
455 end
456 chip drivers/usb/acpi
457 register "desc" = ""USB2 Type-A Port A0 (DB)""
458 register "type" = "UPC_TYPE_A"
459 register "use_custom_pld" = "true"
460 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
461 device ref usb2_port3 on end
462 end
463 chip drivers/usb/acpi
464 register "desc" = ""USB2 Type-A Port A1 (DB)""
465 register "type" = "UPC_TYPE_A"
466 register "use_custom_pld" = "true"
467 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
468 device ref usb2_port4 on end
469 end
470 chip drivers/usb/acpi
471 register "desc" = ""USB2 Camera""
472 register "type" = "UPC_TYPE_INTERNAL"
473 device ref usb2_port6 on end
474 end
475 chip drivers/usb/acpi
476 register "desc" = ""USB2 Bluetooth""
477 register "type" = "UPC_TYPE_INTERNAL"
478 register "reset_gpio" =
479 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
480 device ref usb2_port8 on end
481 end
482 chip drivers/usb/acpi
483 register "desc" = ""USB2 Bluetooth""
484 register "type" = "UPC_TYPE_INTERNAL"
485 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
486 device ref usb2_port10 on end
487 end
488 chip drivers/usb/acpi
489 register "desc" = ""USB3 Type-A Port A0 (MLB)""
490 register "type" = "UPC_TYPE_USB3_A"
491 register "use_custom_pld" = "true"
492 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
493 device ref usb3_port1 on end
494 end
495 chip drivers/usb/acpi
496 register "desc" = ""USB3 Type-A Port A1 (DB)""
497 register "type" = "UPC_TYPE_USB3_A"
498 register "use_custom_pld" = "true"
499 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
500 device ref usb3_port2 on end
501 end
502 end
503 end
504 end
505 device ref hda on
506 chip drivers/sof
507 register "spkr_tplg" = "rt5650_sp"
508 register "jack_tplg" = "rt5650_hp"
509 register "mic_tplg" = "_2ch_pdm0"
510 device generic 0 on end
511 end
512 end
513 end
514
515 end
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