src/mainboard/google/brya/variants/glassway/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <soc/gpio.h>
   6
   7 /* Pad configuration in ramstage for glassway */
   8 static const struct pad_config override_gpio_table[] = {
   9         /* A8  : WWAN_RF_DISABLE_ODL */
  10         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  11         /* D3  : ISH_GP3 ==> NC */
  12         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  13         /* D6  : WWAN_EN */
  14         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  15         /* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
  16         PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
  17         /* D15 : ISH_UART0_RTS# ==> NC */
  18         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  19         /* D16 : ISH_UART0_CTS# ==> NC */
  20         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  21         /* D17 : PCIE SLOT1 WAKE N */
  22         PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  23         /* E4 : SDD_STRAP1 */
  24         PAD_CFG_GPI(GPP_E4, NONE, DEEP),
  25         /* E5 : SDD_STRAP2 */
  26         PAD_CFG_GPI(GPP_E5, NONE, DEEP),
  27         /* F12 : WWAN_RST_L */
  28         PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
  29         /* H19 : SOC_I2C_SUB_INT_ODL */
  30         PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
  31         /* H22 : IMGCLKOUT3 ==> NC */
  32         PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG),
  33         /* H23 : WWAN_SAR_DETECT_ODL */
  34         PAD_CFG_GPO(GPP_H23, 1, DEEP),
  35         /* R4 : I2S2_SCLK ==> DMIC_UCAM_CLK_R */
  36         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
  37         /* R5 : I2S2_SFRM ==> DMIC_UCAM_DATA_R */
  38         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
  39         /* R6 : DMIC_CLK_A_1A ==> NC */
  40         PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
  41
  42         /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
  43         /* BT_I2S_BCLK */
  44         PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
  45         /* BT_I2S_SYNC */
  46         PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
  47         /* BT_I2S_SDO */
  48         PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
  49         /* BT_I2S_SDI */
  50         PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
  51         /* SSP2_SCLK */
  52         PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
  53         /* SSP2_SFRM */
  54         PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
  55         /* SSP_TXD */
  56         PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
  57         /* SSP_RXD */
  58         PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
  59 };
  60
  61 /* Early pad configuration in bootblock for glassway */
  62 static const struct pad_config early_gpio_table[] = {
  63         /* F12 : GSXDOUT ==> WWAN_RST_L */
  64         PAD_CFG_GPO(GPP_F12, 0, DEEP),
  65         /* H12 : UART0_RTS# ==> SD_PERST_L */
  66         PAD_CFG_GPO(GPP_H12, 0, DEEP),
  67         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
  68         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  69         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  70         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  71         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
  72         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
  73         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
  74         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
  75         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
  76         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
  77         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
  78         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
  79         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
  80         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
  81         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
  82         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
  83         /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
  84         PAD_CFG_GPO(GPP_H13, 1, DEEP),
  85 };
  86
  87 static const struct pad_config romstage_gpio_table[] = {
  88         /* Enable touchscreen, hold in reset */
  89         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
  90         PAD_CFG_GPO(GPP_C0, 1, DEEP),
  91         /* C1  : SMBDATA ==> USI_RST_L */
  92         PAD_CFG_GPO(GPP_C1, 0, DEEP),
  93         /* C6  : SML1CLK ==> TCHSCR_REPORT_EN */
  94         PAD_CFG_GPO(GPP_C6, 0, DEEP),
  95         /* H12 : UART0_RTS# ==> SD_PERST_L */
  96         PAD_CFG_GPO(GPP_H12, 1, DEEP),
  97 };
  98
  99 const struct pad_config *variant_gpio_override_table(size_t *num)
 100 {
 101         *num = ARRAY_SIZE(override_gpio_table);
 102         return override_gpio_table;
 103 }
 104
 105 const struct pad_config *variant_early_gpio_table(size_t *num)
 106 {
 107         *num = ARRAY_SIZE(early_gpio_table);
 108         return early_gpio_table;
 109 }
 110
 111
 112 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 113 {
 114         *num = ARRAY_SIZE(romstage_gpio_table);
 115         return romstage_gpio_table;
 116 }