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mb/google/fatcat: config GPP_F23 as ISH gpio pin
[coreboot2.git] / src / mainboard / google / brya / variants / gothrax / overridetree.cb
blob49078fe6edcae56a23da0e56734c0cc8f1a89832
1 fw_config
2 field DB_USB 0 1
3 option DB_NONE 0
4 option DB_C_A 1
5 option DB_C_A_LTE 2
6 option DB_A 3
7 end
8 field THERMAL_SOLUTION 2
9 option THERMAL_SOLUTION_PASSIVE 0
10 option THERMAL_SOLUTION_ACTIVE 1
11 end
12 field WLAN 3 4
13 option WLAN_MT7921_AZUREWAVE 0
14 option WLAN_AX211_Intel 1
15 end
16 field AUDIO 5 6
17 option AUDIO_ALC1019_ALC5682IVS 0
18 end
19 field STYLUS 7
20 option STYLUS_ABSENT 0
21 option STYLUS_PRESENT 1
22 end
23 field WFC 8
24 option WFC_PRESENT 0
25 option WFC_ABSENT 1
26 end
27 field TOUCH_PANEL 9
28 option TOUCH_PANEL_ENABLE 0
29 option TOUCH_PANEL_DISABLE 1
30 end
31 end
32
33 chip soc/intel/alderlake
34 register "sagv" = "SaGv_Enabled"
35
36 # EMMC Tx CMD Delay
37 # Refer to EDS-Vol2-42.3.7.
38 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
39 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
40 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
41
42 # EMMC TX DATA Delay 1
43 # Refer to EDS-Vol2-42.3.8.
44 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
45 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
46 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
47
48 # EMMC TX DATA Delay 2
49 # Refer to EDS-Vol2-42.3.9.
50 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
51 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
52 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
53 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
54 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
55
56 # EMMC RX CMD/DATA Delay 1
57 # Refer to EDS-Vol2-42.3.10.
58 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
59 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
60 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
61 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
62 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
63
64 # EMMC RX CMD/DATA Delay 2
65 # Refer to EDS-Vol2-42.3.12.
66 # [17:16] stands for Rx Clock before Output Buffer,
67 # 00: Rx clock after output buffer,
68 # 01: Rx clock before output buffer,
69 # 10: Automatic selection based on working mode.
70 # 11: Reserved
71 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
72 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
73 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10005"
74
75 # EMMC Rx Strobe Delay
76 # Refer to EDS-Vol2-42.3.11.
77 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
78 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
79 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"
80
81 # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
82 # Bit 2 - C1 has a redriver which does SBU muxing.
83 # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
84 register "tcss_aux_ori" = "5"
85
86 register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
87 register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
88
89 # Configure external V1P05/Vnn/VnnSx Rails
90 register "ext_fivr_settings" = "{
91 .configure_ext_fivr = 1,
92 .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
93 .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
94 .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
95 .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
96 .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
97 .v1p05_voltage_mv = 1050,
98 .vnn_voltage_mv = 780,
99 .vnn_sx_voltage_mv = 1050,
100 .v1p05_icc_max_ma = 500,
101 .vnn_icc_max_ma = 500,
102 }"
103
104 # Intel Common SoC Config
105 #+-------------------+---------------------------+
106 #| Field | Value |
107 #+-------------------+---------------------------+
108 #| I2C0 | TPM. Early init is |
109 #| | required to set up a BAR |
110 #| | for TPM communication |
111 #| I2C1 | Touchscreen |
112 #| I2C2 | Sub-board(PSensor)/WCAM |
113 #| I2C3 | Audio |
114 #| I2C5 | Trackpad |
115 #+-------------------+---------------------------+
116 register "common_soc_config" = "{
117 .i2c[0] = {
118 .early_init = 1,
119 .speed = I2C_SPEED_FAST_PLUS,
120 .speed_config[0] = {
121 .speed = I2C_SPEED_FAST_PLUS,
122 .scl_lcnt = 55,
123 .scl_hcnt = 30,
124 .sda_hold = 7,
125 }
126 },
127 .i2c[1] = {
128 .speed = I2C_SPEED_FAST,
129 .speed_config[0] = {
130 .speed = I2C_SPEED_FAST,
131 .scl_lcnt = 160,
132 .scl_hcnt = 79,
133 .sda_hold = 7,
134 }
135 },
136 .i2c[2] = {
137 .speed = I2C_SPEED_FAST,
138 .speed_config[0] = {
139 .speed = I2C_SPEED_FAST,
140 .scl_lcnt = 157,
141 .scl_hcnt = 79,
142 .sda_hold = 7,
143 }
144 },
145 .i2c[3] = {
146 .speed = I2C_SPEED_FAST,
147 .speed_config[0] = {
148 .speed = I2C_SPEED_FAST,
149 .scl_lcnt = 157,
150 .scl_hcnt = 79,
151 .sda_hold = 7,
152 }
153 },
154 .i2c[5] = {
155 .speed = I2C_SPEED_FAST,
156 .speed_config[0] = {
157 .speed = I2C_SPEED_FAST,
158 .scl_lcnt = 152,
159 .scl_hcnt = 79,
160 .sda_hold = 7,
161 }
162 },
163 }"
164
165 device domain 0 on
166 device ref dtt on
167 chip drivers/intel/dptf
168 ## sensor information
169 register "options.tsr[0].desc" = ""Memory""
170 register "options.tsr[1].desc" = ""Charger""
171 register "options.tsr[2].desc" = ""Ambient""
172
173 # TODO: below values are initial reference values only
174 ## Passive Policy
175 register "policies.passive" = "{
176 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
177 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
178 [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
179 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
180 }"
181
182 ## Critical Policy
183 register "policies.critical" = "{
184 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
185 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
186 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
187 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
188 }"
189
190 register "controls.power_limits" = "{
191 .pl1 = {
192 .min_power = 3000,
193 .max_power = 6000,
194 .time_window_min = 28 * MSECS_PER_SEC,
195 .time_window_max = 32 * MSECS_PER_SEC,
196 .granularity = 200
197 },
198 .pl2 = {
199 .min_power = 25000,
200 .max_power = 25000,
201 .time_window_min = 28 * MSECS_PER_SEC,
202 .time_window_max = 32 * MSECS_PER_SEC,
203 .granularity = 1000
204 }
205 }"
206
207 ## Charger Performance Control (Control, mA)
208 register "controls.charger_perf" = "{
209 [0] = { 255, 1700 },
210 [1] = { 24, 1500 },
211 [2] = { 16, 1000 },
212 [3] = { 8, 500 }
213 }"
214
215 device generic 0 on end
216 end
217 end
218 device ref i2c1 on
219 chip drivers/i2c/hid
220 register "generic.hid" = ""ELAN7B13""
221 register "generic.desc" = ""ELAN Touchscreen""
222 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
223 register "generic.detect" = "1"
224 register "generic.reset_gpio" =
225 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
226 register "generic.reset_delay_ms" = "300"
227 register "generic.reset_off_delay_ms" = "2"
228 register "generic.enable_gpio" =
229 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
230 register "generic.enable_delay_ms" = "6"
231 register "generic.has_power_resource" = "1"
232 register "hid_desc_reg_offset" = "0x01"
233 device i2c 0x10 on
234 probe TOUCH_PANEL TOUCH_PANEL_ENABLE
235 end
236 end
237 chip drivers/i2c/hid
238 register "generic.hid" = ""ILI2901""
239 register "generic.desc" = ""ILI Touchscreen""
240 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
241 register "generic.detect" = "1"
242 register "generic.reset_gpio" =
243 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
244 register "generic.reset_delay_ms" = "200"
245 register "generic.reset_off_delay_ms" = "2"
246 register "generic.enable_gpio" =
247 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
248 register "generic.enable_delay_ms" = "6"
249 register "generic.has_power_resource" = "1"
250 register "hid_desc_reg_offset" = "0x01"
251 device i2c 0x41 on
252 probe TOUCH_PANEL TOUCH_PANEL_ENABLE
253 end
254 end
255 end
256 device ref i2c2 on
257 chip drivers/i2c/sx9324
258 register "desc" = ""SAR2 Proximity Sensor""
259 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
260 register "speed" = "I2C_SPEED_FAST"
261 register "uid" = "1"
262 register "reg_gnrl_ctrl0" = "0x16"
263 register "reg_gnrl_ctrl1" = "0x21"
264 register "reg_afe_ctrl0" = "0x20"
265 register "reg_afe_ctrl1" = "0x10"
266 register "reg_afe_ctrl2" = "0x00"
267 register "reg_afe_ctrl3" = "0x01"
268 register "reg_afe_ctrl4" = "0x46"
269 register "reg_afe_ctrl5" = "0x00"
270 register "reg_afe_ctrl6" = "0x00"
271 register "reg_afe_ctrl7" = "0x07"
272 register "reg_afe_ctrl8" = "0x12"
273 register "reg_afe_ctrl9" = "0x0f"
274 register "reg_prox_ctrl0" = "0x12"
275 register "reg_prox_ctrl1" = "0x12"
276 register "reg_prox_ctrl2" = "0x90"
277 register "reg_prox_ctrl3" = "0x60"
278 register "reg_prox_ctrl4" = "0x0c"
279 register "reg_prox_ctrl5" = "0x12"
280 register "reg_prox_ctrl6" = "0x3c"
281 register "reg_prox_ctrl7" = "0x58"
282 register "reg_adv_ctrl0" = "0x00"
283 register "reg_adv_ctrl1" = "0x00"
284 register "reg_adv_ctrl2" = "0x00"
285 register "reg_adv_ctrl3" = "0x00"
286 register "reg_adv_ctrl4" = "0x00"
287 register "reg_adv_ctrl5" = "0x05"
288 register "reg_adv_ctrl6" = "0x00"
289 register "reg_adv_ctrl7" = "0x00"
290 register "reg_adv_ctrl8" = "0x00"
291 register "reg_adv_ctrl9" = "0x00"
292 register "reg_adv_ctrl10" = "0x5c"
293 register "reg_adv_ctrl11" = "0x52"
294 register "reg_adv_ctrl12" = "0xb5"
295 register "reg_adv_ctrl13" = "0x00"
296 register "reg_adv_ctrl14" = "0x80"
297 register "reg_adv_ctrl15" = "0x0c"
298 register "reg_adv_ctrl16" = "0x38"
299 register "reg_adv_ctrl17" = "0x56"
300 register "reg_adv_ctrl18" = "0x33"
301 register "reg_adv_ctrl19" = "0xf0"
302 register "reg_adv_ctrl20" = "0xf0"
303
304 register "ph0_pin" = "{1, 3, 3}"
305 register "ph1_pin" = "{3, 2, 1}"
306 register "ph2_pin" = "{3, 3, 1}"
307 register "ph3_pin" = "{1, 3, 3}"
308 register "ph01_resolution" = "512"
309 register "ph23_resolution" = "1024"
310 register "startup_sensor" = "1"
311 register "ph01_proxraw_strength" = "2"
312 register "ph23_proxraw_strength" = "2"
313 register "avg_pos_strength" = "256"
314 register "cs_idle_sleep" = ""gnd""
315 register "int_comp_resistor" = ""lowest""
316 register "input_precharge_resistor_ohms" = "4000"
317 register "input_analog_gain" = "3"
318 device i2c 28 on
319 probe DB_USB DB_C_A_LTE
320 end
321 end
322 end
323 device ref i2c3 on
324 chip drivers/i2c/generic
325 register "hid" = ""RTL5682""
326 register "name" = ""RT58""
327 register "desc" = ""Headset Codec""
328 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
329 # Set the jd_src to RT5668_JD1 for jack detection
330 register "property_count" = "1"
331 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
332 register "property_list[0].name" = ""realtek,jd-src""
333 register "property_list[0].integer" = "1"
334 device i2c 1a on end
335 end
336 chip drivers/generic/alc1015
337 register "hid" = ""RTL1019""
338 register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
339 device generic 0 on end
340 end
341 end
342
343 device ref i2c5 on
344 chip drivers/i2c/hid
345 register "generic.hid" = ""PNP0C50""
346 register "generic.desc" = ""PIXART Touchpad""
347 register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
348 register "generic.wake" = "GPE0_DW2_14"
349 register "generic.detect" = "1"
350 register "hid_desc_reg_offset" = "0x01"
351 device i2c 15 on end
352 end
353 end
354 device ref pcie_rp4 on
355 # PCIe 4 WLAN
356 register "pch_pcie_rp[PCH_RP(4)]" = "{
357 .clk_src = 2,
358 .clk_req = 2,
359 .flags = PCIE_RP_LTR | PCIE_RP_AER,
360 }"
361 chip drivers/wifi/generic
362 register "wake" = "GPE0_DW1_03"
363 register "add_acpi_dma_property" = "true"
364 device pci 00.0 on end
365 end
366 end
367 device ref pcie_rp7 on
368 # Enable SD Card PCIe 7 using clk 3
369 register "pch_pcie_rp[PCH_RP(7)]" = "{
370 .clk_src = 3,
371 .clk_req = 3,
372 .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
373 }"
374 chip soc/intel/common/block/pcie/rtd3
375 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
376 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
377 register "srcclk_pin" = "3"
378 device generic 0 on end
379 end
380 end
381 device ref pch_espi on
382 chip ec/google/chromeec
383 use conn0 as mux_conn[0]
384 use conn1 as mux_conn[1]
385 device pnp 0c09.0 on end
386 end
387 end
388 device ref pmc hidden
389 chip drivers/intel/pmc_mux
390 device generic 0 on
391 chip drivers/intel/pmc_mux/conn
392 use usb2_port1 as usb2_port
393 use tcss_usb3_port1 as usb3_port
394 device generic 0 alias conn0 on end
395 end
396 chip drivers/intel/pmc_mux/conn
397 use usb2_port2 as usb2_port
398 use tcss_usb3_port2 as usb3_port
399 device generic 1 alias conn1 on end
400 end
401 end
402 end
403 end
404 device ref tcss_xhci on
405 chip drivers/usb/acpi
406 device ref tcss_root_hub on
407 chip drivers/usb/acpi
408 register "desc" = ""USB3 Type-C Port C0 (MLB)""
409 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
410 register "use_custom_pld" = "true"
411 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
412 device ref tcss_usb3_port1 on end
413 end
414 chip drivers/usb/acpi
415 register "desc" = ""USB3 Type-C Port C1 (DB)""
416 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
417 register "use_custom_pld" = "true"
418 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
419 device ref tcss_usb3_port2 on
420 probe DB_USB DB_C_A
421 probe DB_USB DB_C_A_LTE
422 end
423 end
424 end
425 end
426 end
427 device ref xhci on
428 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
429 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC
430 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
431 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
432 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1
433
434 chip drivers/usb/acpi
435 device ref xhci_root_hub on
436 chip drivers/usb/acpi
437 register "desc" = ""USB2 Type-C Port C0 (MLB)""
438 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
439 register "use_custom_pld" = "true"
440 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
441 device ref usb2_port1 on end
442 end
443 chip drivers/usb/acpi
444 register "desc" = ""USB2 Type-C Port C1 (DB)""
445 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
446 register "use_custom_pld" = "true"
447 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
448 device ref usb2_port2 on
449 probe DB_USB DB_C_A
450 probe DB_USB DB_C_A_LTE
451 end
452 end
453 chip drivers/usb/acpi
454 register "desc" = ""USB2 Type-A Port A0 (MLB)""
455 register "type" = "UPC_TYPE_A"
456 register "use_custom_pld" = "true"
457 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
458 device ref usb2_port3 on end
459 end
460 chip drivers/usb/acpi
461 register "desc" = ""USB2 Type-A Port A1 (DB)""
462 register "type" = "UPC_TYPE_A"
463 register "use_custom_pld" = "true"
464 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
465 device ref usb2_port4 on end
466 end
467 chip drivers/usb/acpi
468 register "desc" = ""USB2 WWAN""
469 register "type" = "UPC_TYPE_INTERNAL"
470 device ref usb2_port5 on
471 probe DB_USB DB_C_A_LTE
472 end
473 end
474 chip drivers/usb/acpi
475 register "desc" = ""USB2 UFC""
476 register "type" = "UPC_TYPE_INTERNAL"
477 device ref usb2_port6 on end
478 end
479 chip drivers/usb/acpi
480 register "desc" = ""USB2 WFC""
481 register "type" = "UPC_TYPE_INTERNAL"
482 device ref usb2_port7 on
483 probe WFC WFC_PRESENT
484 end
485 end
486 chip drivers/usb/acpi
487 register "desc" = ""USB2 Bluetooth""
488 register "type" = "UPC_TYPE_INTERNAL"
489 register "reset_gpio" =
490 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
491 device ref usb2_port8 on end
492 end
493 chip drivers/usb/acpi
494 register "desc" = ""CNVi Bluetooth""
495 register "type" = "UPC_TYPE_INTERNAL"
496 register "reset_gpio" =
497 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
498 device ref usb2_port10 on end
499 end
500 chip drivers/usb/acpi
501 register "desc" = ""USB3 Type-A Port A0 (MLB)""
502 register "type" = "UPC_TYPE_USB3_A"
503 register "use_custom_pld" = "true"
504 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
505 device ref usb3_port1 on end
506 end
507 chip drivers/usb/acpi
508 register "desc" = ""USB3 Type-A Port A1 (DB)""
509 register "type" = "UPC_TYPE_USB3_A"
510 register "use_custom_pld" = "true"
511 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
512 device ref usb3_port2 on end
513 end
514 chip drivers/usb/acpi
515 register "desc" = ""USB3 WWAN""
516 register "type" = "UPC_TYPE_INTERNAL"
517 device ref usb3_port3 on
518 probe DB_USB DB_C_A_LTE
519 end
520 end
521 end
522 end
523 end
524 device ref hda on
525 chip drivers/sof
526 register "spkr_tplg" = "rt1019"
527 register "jack_tplg" = "rt5682"
528 register "mic_tplg" = "_2ch_pdm0"
529 device generic 0 on end
530 end
531 end
532 end
533 end
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