soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / mainboard / google / brya / variants / marasov / Makefile.mk
blob70f64013b4989edd1fa138ddb4b1eb444d56d4f2
1 # SPDX-License-Identifier: GPL-2.0-only
2 bootblock-y += gpio.c
4 romstage-y += gpio.c
5 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
7 romstage-y += memory.c
9 ramstage-y += gpio.c
11 ramstage-y += variant.c