src/mainboard/google/brya/variants/moli/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <boardid.h>
   7 #include <gpio.h>
   8
   9 /* Pad configuration in ramstage */
  10 static const struct pad_config override_gpio_table[] = {
  11         /* A14 : USB_OC1# ==> NC */
  12         PAD_NC(GPP_A14, NONE),
  13         /* A19 : DDSP_HPD1 ==> NC */
  14         PAD_NC(GPP_A19, NONE),
  15         /* A20 : DDSP_HPD2 ==> DDIC_DP_HPD4 */
  16         PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
  17         /* A21 : DDPC_CTRCLK ==> DDIC_DP_CTRCLK */
  18         PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
  19         /* A22 : DDPC_CTRLDATA ==> DDIC_DP_CTRLDATA */
  20         PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
  21
  22         /* B2  : VRALERT# ==> NC */
  23         PAD_NC(GPP_B2, NONE),
  24         /* B3  : PROC_GP2 ==> EMMC_PERST_L */
  25         PAD_CFG_GPO(GPP_B3, 1, DEEP),
  26
  27         /* D6  : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */
  28         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
  29         /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */
  30         PAD_CFG_GPO(GPP_D14, 1, DEEP),
  31
  32         /* E1  : THC0_SPI1_IO2 ==> B2B_HDMICARD_DETN */
  33         PAD_CFG_GPI(GPP_E1, NONE, DEEP),
  34         /* E2  : THC0_SPI1_IO3 ==> B2B_DPCARD_DETN */
  35         PAD_CFG_GPI(GPP_E2, NONE, DEEP),
  36         /* E20 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */
  37         PAD_CFG_GPO(GPP_E20, 1, DEEP),
  38         /* E21 : DDP2_CTRLDATA ==> NC */
  39         PAD_NC(GPP_E21, NONE),
  40
  41         /* H19 : SRCCLKREQ4# ==> LAN_I225V_CLKREQ_ODL */
  42         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
  43
  44         /* R6 : I2S2_TXD ==> NC */
  45         PAD_NC(GPP_R6, NONE),
  46         /* R7 : I2S2_RXD ==> NC */
  47         PAD_NC(GPP_R7, NONE),
  48
  49         /* GPD11: LANPHYC ==> LAN_DISABLE_N */
  50         PAD_CFG_GPO(GPD11, 0, DEEP),
  51 };
  52
  53
  54 static const struct pad_config override_gpio_table_id2[] = {
  55         /* A14 : USB_OC1# ==> NC */
  56         PAD_NC(GPP_A14, NONE),
  57         /* A19 : DDSP_HPD1 ==> NC */
  58         PAD_NC(GPP_A19, NONE),
  59         /* A20 : DDSP_HPD2 ==> DDIC_DP_HPD4 */
  60         PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
  61         /* A21 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */
  62         PAD_CFG_GPO(GPP_A21, 1, DEEP),
  63         /* A22 : DDPC_CTRLDATA ==> NC */
  64         PAD_NC(GPP_A22, NONE),
  65
  66         /* B2  : VRALERT# ==> NC */
  67         PAD_NC(GPP_B2, NONE),
  68         /* B3  : PROC_GP2 ==> EMMC_PERST_L */
  69         PAD_CFG_GPO(GPP_B3, 1, DEEP),
  70
  71         /* D6  : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */
  72         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
  73         /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */
  74         PAD_CFG_GPO(GPP_D14, 1, DEEP),
  75
  76         /* E1  : THC0_SPI1_IO2 ==> B2B_HDMICARD_DETN */
  77         PAD_CFG_GPI(GPP_E1, NONE, DEEP),
  78         /* E2  : THC0_SPI1_IO3 ==> B2B_DPCARD_DETN */
  79         PAD_CFG_GPI(GPP_E2, NONE, DEEP),
  80         /* E20 : DDP2_CTRLCLK ==> DDIC_DP_CTRCLK */
  81         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
  82         /* E21 : DDP2_CTRLDATA ==> DDIC_DP_CTRLDATA */
  83         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
  84
  85         /* H19 : SRCCLKREQ4# ==> LAN_I225V_CLKREQ_ODL */
  86         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
  87
  88         /* R6 : I2S2_TXD ==> NC */
  89         PAD_NC(GPP_R6, NONE),
  90         /* R7 : I2S2_RXD ==> NC */
  91         PAD_NC(GPP_R7, NONE),
  92
  93         /* GPD11: LANPHYC ==> LAN_DISABLE_N */
  94         PAD_CFG_GPO(GPD11, 0, DEEP),
  95 };
  96
  97
  98 /* Early pad configuration in bootblock */
  99 static const struct pad_config early_gpio_table[] = {
 100         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 101         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 102         /* B3  : PROC_GP2 ==> EMMC_PERST_L */
 103         PAD_CFG_GPO(GPP_B3, 0, DEEP),
 104         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 105         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 106         /*
 107          * D1  : ISH_GP1 ==> FP_RST_ODL
 108          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 109          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 110          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 111          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 112          * FPMCU not working after a S3 resume. This is a known issue.
 113          */
 114         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 115         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 116         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 117         /* D18 : UART1_TXD ==> SD_PE_RST_L */
 118         PAD_CFG_GPO(GPP_D18, 0, PLTRST),
 119         /* E15 : RSVD_TP ==> PCH_WP_OD */
 120         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 121         /* E20 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */
 122         PAD_CFG_GPO(GPP_E20, 1, DEEP),
 123         /* F14 : GSXDIN ==> EN_PP3300_SSD */
 124         PAD_CFG_GPO(GPP_F14, 1, DEEP),
 125         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 126         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 127         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 128         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 129         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 130         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 131         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 132         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 133         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 134         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 135         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 136         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 137
 138         /* CPU PCIe VGPIO for PEG60 */
 139         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 140         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 141         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 142         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 143         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 144         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 145         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 146         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 147         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 148         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 149         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 150         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 151         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 152         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 153         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 154         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 155         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 156         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 157         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 158         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 159 };
 160
 161
 162 /* Early pad configuration in bootblock */
 163 static const struct pad_config early_gpio_table_id2[] = {
 164         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 165         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 166         /* A21 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */
 167         PAD_CFG_GPO(GPP_A21, 1, DEEP),
 168         /* B3  : PROC_GP2 ==> EMMC_PERST_L */
 169         PAD_CFG_GPO(GPP_B3, 0, DEEP),
 170         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 171         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 172         /*
 173          * D1  : ISH_GP1 ==> FP_RST_ODL
 174          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 175          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 176          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 177          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 178          * FPMCU not working after a S3 resume. This is a known issue.
 179          */
 180         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 181         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 182         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 183         /* D18 : UART1_TXD ==> SD_PE_RST_L */
 184         PAD_CFG_GPO(GPP_D18, 0, PLTRST),
 185         /* E15 : RSVD_TP ==> PCH_WP_OD */
 186         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 187         /* F14 : GSXDIN ==> EN_PP3300_SSD */
 188         PAD_CFG_GPO(GPP_F14, 1, DEEP),
 189         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 190         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 191         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 192         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 193         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 194         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 195         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 196         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 197         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 198         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 199         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 200         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 201
 202         /* CPU PCIe VGPIO for PEG60 */
 203         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 204         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 205         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 206         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 207         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 208         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 209         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 210         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 211         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 212         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 213         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 214         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 215         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 216         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 217         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 218         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 219         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 220         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 221         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 222         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 223 };
 224 static const struct pad_config romstage_gpio_table[] = {
 225         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 226         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 227         /* D18 : UART1_TXD ==> SD_PE_RST_L */
 228         PAD_CFG_GPO(GPP_D18, 1, DEEP),
 229 };
 230
 231 const struct pad_config *variant_gpio_override_table(size_t *num)
 232 {
 233         const uint32_t board_ver = board_id();
 234         if (board_ver <= 1) {
 235                 *num = ARRAY_SIZE(override_gpio_table);
 236                 return override_gpio_table;
 237         }
 238         *num = ARRAY_SIZE(override_gpio_table_id2);
 239         return override_gpio_table_id2;
 240 }
 241
 242 const struct pad_config *variant_early_gpio_table(size_t *num)
 243 {
 244         const uint32_t board_ver = board_id();
 245         if (board_ver <= 1) {
 246                 *num = ARRAY_SIZE(early_gpio_table);
 247                 return early_gpio_table;
 248         }
 249         *num = ARRAY_SIZE(early_gpio_table_id2);
 250         return early_gpio_table_id2;
 251 }
 252
 253 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 254 {
 255         *num = ARRAY_SIZE(romstage_gpio_table);
 256         return romstage_gpio_table;
 257 }