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soc/intel/xeon_sp: Allow OS to control LTR and AER
[coreboot2.git] / src / mainboard / google / brya / variants / moli / overridetree.cb
blob3397d0c2117f614a1c5dcbb486705746b0082631
1 fw_config
2 field USBC0_RETIMER 2 3
3 option USBC0_RETIMER_ABSENT 0
4 option USBC0_RETIMER_PRESENT 1
5 end
6 field STORAGE 4 5
7 option STORAGE_UNKNOWN 0
8 option STORAGE_NVME 1
9 option STORAGE_EMMC 2
10 end
11 field AUDIO 6
12 option AUDIO_UNKNOWN 0
13 option NAU88L25B_I2S 1
14 end
15 end
16 chip soc/intel/alderlake
17 # As per Intel Advisory doc#723158, the change is required to prevent possible
18 # display flickering issue.
19 register "usb2_phy_sus_pg_disable" = "1"
20 # Enable HDMI2 in PortA, HDMI1 in PortB, HDMI/DP in Port2
21 register "ddi_ports_config" = "{
22 [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
23 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
24 [DDI_PORT_1] = DDI_ENABLE_HPD,
25 [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
26 [DDI_PORT_3] = DDI_ENABLE_HPD,
27 }"
28 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port2
29 register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2 Port3
30 register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # Enable USB2 Port4
31 register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port9
32 register "usb3_ports[2]" = "{
33 .enable = 1,
34 .ocpin = OC_SKIP,
35 .tx_de_emp = 0x2B,
36 .tx_downscale_amp = 0x00,
37 }" # Type-A port A2
38 register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3
39
40 # Bitmap for Wake Enable on USB attach/detach
41 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(4) |
42 USB_PORT_WAKE_ENABLE(6) |
43 USB_PORT_WAKE_ENABLE(7) |
44 USB_PORT_WAKE_ENABLE(8)"
45 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
46 USB_PORT_WAKE_ENABLE(2) |
47 USB_PORT_WAKE_ENABLE(3) |
48 USB_PORT_WAKE_ENABLE(4)"
49
50 register "tcc_offset" = "0" # TCC of 100C
51 register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
52 .tdp_pl1_override = 55,
53 }"
54 register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
55 .tdp_pl1_override = 64,
56 }"
57 device domain 0 on
58 device ref dtt on
59 chip drivers/intel/dptf
60 ## sensor information
61 register "options.tsr[0].desc" = ""SSD""
62 register "options.tsr[1].desc" = ""CPU_VR""
63 register "options.tsr[2].desc" = ""DIMM""
64
65
66 ## Passive Policy
67 register "policies.passive" = "{
68 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
69 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
70 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
71 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
72 }"
73
74 ## Critical Policy
75 register "policies.critical" = "{
76 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
77 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
78 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
79 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
80 }"
81
82 register "controls.power_limits" = "{
83 .pl1 = {
84 .min_power = 15000,
85 .max_power = 55000,
86 .time_window_min = 28 * MSECS_PER_SEC,
87 .time_window_max = 32 * MSECS_PER_SEC,
88 .granularity = 200,
89 },
90 .pl2 = {
91 .min_power = 55000,
92 .max_power = 55000,
93 .time_window_min = 28 * MSECS_PER_SEC,
94 .time_window_max = 32 * MSECS_PER_SEC,
95 .granularity = 1000,
96 }
97 }"
98
99 register "oem_data.oem_variables" = "{
100 [0] = 0x1
101 }"
102
103 device generic 0 alias dptf_policy on end
104 end
105 end
106 device ref tcss_dma0 on
107 chip drivers/intel/usb4/retimer
108 register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
109 use tcss_usb3_port1 as dfp[0].typec_port
110 device generic 0 on end
111 end
112 end
113 device ref tcss_dma1 on
114 chip drivers/intel/usb4/retimer
115 register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
116 use tcss_usb3_port3 as dfp[0].typec_port
117 device generic 0 on end
118 end
119 end # USB4 Port
120 device ref pcie4_0 on
121 # Enable CPU PCIE RP 1 using CLK 0
122 register "cpu_pcie_rp[CPU_RP(1)]" = "{
123 .clk_req = 0,
124 .clk_src = 0,
125 .flags = PCIE_RP_LTR | PCIE_RP_AER,
126 }"
127 probe STORAGE STORAGE_NVME
128 probe STORAGE STORAGE_UNKNOWN
129 end # SSD
130 device ref cnvi_wifi on
131 chip drivers/wifi/generic
132 register "wake" = "GPE0_PME_B0"
133 device generic 0 on end
134 end
135 end # WiFi
136 device ref i2c0 on
137 chip drivers/i2c/nau8825
138 register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
139 register "jkdet_enable" = "1"
140 register "jkdet_pull_enable" = "0"
141 register "jkdet_pull_up" = "0"
142 register "jkdet_polarity" = "1" # ActiveLow
143 register "vref_impedance" = "2" # 125kOhm
144 register "micbias_voltage" = "6" # 2.754
145 register "sar_threshold_num" = "4"
146 register "sar_threshold[0]" = "0x0C"
147 register "sar_threshold[1]" = "0x1C"
148 register "sar_threshold[2]" = "0x38"
149 register "sar_threshold[3]" = "0x60"
150 register "sar_hysteresis" = "1"
151 register "sar_voltage" = "0" # VDDA
152 register "sar_compare_time" = "0" # 500ns
153 register "sar_sampling_time" = "0" # 2us
154 register "short_key_debounce" = "2" # 100ms
155 register "jack_insert_debounce" = "7" # 512ms
156 register "jack_eject_debounce" = "7" # 512ms
157 device i2c 1a on end
158 end
159 end # Audio Nau8825
160 device ref pcie_rp6 on
161 # Enable PCIe-to-i225 bridge PCIe 6 using clk 4
162 register "pch_pcie_rp[PCH_RP(6)]" = "{
163 .clk_src = 4,
164 .clk_req = 4,
165 .flags = PCIE_RP_LTR | PCIE_RP_AER,
166 }"
167 device pci 00.0 on end
168 end # IntelI225V Ethernet NIC
169 device ref pcie_rp7 on
170 chip drivers/net
171 register "customized_leds" = "0x0482"
172 register "wake" = "GPE0_DW0_07"
173 register "device_index" = "0"
174 register "add_acpi_dma_property" = "true"
175 device pci 00.0 on end
176 end
177 end # RTL8111K Ethernet NIC
178 device ref pcie_rp8 on
179 chip soc/intel/common/block/pcie/rtd3
180 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
181 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
182 register "srcclk_pin" = "3"
183 device generic 0 on end
184 end
185 end # SD card
186 device ref pcie_rp9 off end #pcie_rp 9 Empty
187 device ref pcie_rp10 off end #pcie_rp 10 Empty
188 device ref pcie_rp11 off end #pcie_rp 11 Empty
189 device ref pcie_rp12 on
190 chip soc/intel/common/block/pcie/rtd3
191 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
192 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
193 register "srcclk_pin" = "1"
194 register "reset_delay_ms" = "50"
195 register "enable_delay_ms" = "20"
196 device generic 0 alias emmc_rtd3 on
197 probe STORAGE STORAGE_EMMC
198 probe STORAGE STORAGE_UNKNOWN
199 end
200 end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1
201 register "pch_pcie_rp[PCH_RP(12)]" = "{
202 .clk_src = 1,
203 .clk_req = 1,
204 .flags = PCIE_RP_LTR | PCIE_RP_AER,
205 }"
206 probe STORAGE STORAGE_EMMC
207 probe STORAGE STORAGE_UNKNOWN
208 end # BH799BB
209 device ref pch_espi on
210 chip ec/google/chromeec
211 use conn0 as mux_conn[0]
212 use conn1 as mux_conn[1]
213 device pnp 0c09.0 on end
214 end
215 end
216 device ref pmc hidden
217 chip drivers/intel/pmc_mux
218 device generic 0 on
219 chip drivers/intel/pmc_mux/conn
220 use usb2_port1 as usb2_port
221 use tcss_usb3_port1 as usb3_port
222 device generic 0 alias conn0 on end
223 end
224 chip drivers/intel/pmc_mux/conn
225 use usb2_port3 as usb2_port
226 use tcss_usb3_port3 as usb3_port
227 device generic 1 alias conn1 on end
228 end
229 end
230 end
231 end
232 device ref tcss_xhci on
233 chip drivers/usb/acpi
234 device ref tcss_root_hub on
235 chip drivers/usb/acpi
236 register "desc" = ""USB3 Type-C Port C0 (MLB)""
237 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
238 register "use_custom_pld" = "true"
239 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
240 device ref tcss_usb3_port1 on end
241 end
242 chip drivers/usb/acpi
243 register "desc" = ""USB3 Type-C Port C2 (MLB)""
244 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
245 register "use_custom_pld" = "true"
246 register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
247 device ref tcss_usb3_port3 on end
248 end
249 end
250 end
251 end
252 device ref xhci on
253 chip drivers/usb/acpi
254 device ref xhci_root_hub on
255 chip drivers/usb/acpi
256 register "desc" = ""USB2 Type-C Port C0 (MLB)""
257 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
258 register "use_custom_pld" = "true"
259 register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
260 device ref usb2_port1 on end
261 end
262 chip drivers/usb/acpi
263 register "desc" = ""USB2 Type-C Port C2 (MLB)""
264 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
265 register "use_custom_pld" = "true"
266 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))"
267 device ref usb2_port3 on end
268 end
269 chip drivers/usb/acpi
270 register "desc" = ""USB2 Type-A Port A4 (MLB)""
271 register "type" = "UPC_TYPE_A"
272 register "use_custom_pld" = "true"
273 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
274 device ref usb2_port4 on end
275 end
276 chip drivers/usb/acpi
277 register "desc" = ""USB2 NFC""
278 register "type" = "UPC_TYPE_INTERNAL"
279 device ref usb2_port5 on end
280 end
281 chip drivers/usb/acpi
282 register "desc" = ""USB2 Type-A Port A3 (MLB)""
283 register "type" = "UPC_TYPE_A"
284 register "use_custom_pld" = "true"
285 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
286 device ref usb2_port6 on end
287 end
288 chip drivers/usb/acpi
289 register "desc" = ""USB2 Type-A Port A2 (MLB)""
290 register "type" = "UPC_TYPE_A"
291 register "use_custom_pld" = "true"
292 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
293 device ref usb2_port7 on end
294 end
295 chip drivers/usb/acpi
296 register "desc" = ""USB2 Type-A Port A1 (MLB)""
297 register "type" = "UPC_TYPE_A"
298 register "use_custom_pld" = "true"
299 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 1))"
300 device ref usb2_port8 on end
301 end
302 chip drivers/usb/acpi
303 register "desc" = ""USB2 Bluetooth""
304 register "type" = "UPC_TYPE_INTERNAL"
305 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
306 device ref usb2_port10 on end
307 end
308 chip drivers/usb/acpi
309 register "desc" = ""USB3 Type-A Port A1 (MLB)""
310 register "type" = "UPC_TYPE_USB3_A"
311 register "use_custom_pld" = "true"
312 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 2))"
313 device ref usb3_port1 on end
314 end
315 chip drivers/usb/acpi
316 register "desc" = ""USB3 Type-A Port A2 (MLB)""
317 register "type" = "UPC_TYPE_USB3_A"
318 register "use_custom_pld" = "true"
319 register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(6, 1))"
320 device ref usb3_port2 on end
321 end
322 chip drivers/usb/acpi
323 register "desc" = ""USB3 Type-A Port A3 (MLB)""
324 register "type" = "UPC_TYPE_USB3_A"
325 register "use_custom_pld" = "true"
326 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))"
327 device ref usb3_port3 on end
328 end
329 chip drivers/usb/acpi
330 register "desc" = ""USB3 Type-A Port A4 (MLB)""
331 register "type" = "UPC_TYPE_USB3_A"
332 register "use_custom_pld" = "true"
333 register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
334 device ref usb3_port4 on end
335 end
336 end
337 end
338 end # USB2 and USB3 Port
339 end
340
341 end
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