src/mainboard/google/brya/variants/nova/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <gpio.h>
   6
   7 static const struct mb_cfg baseboard_memcfg = {
   8         .type = MEM_TYPE_LP4X,
   9
  10         .rcomp = {
  11                 /* Baseboard uses only 100ohm Rcomp resistors */
  12                 .resistor = 100,
  13
  14                 /* Baseboard Rcomp target values */
  15                 .targets = {40, 30, 30, 30, 30},
  16         },
  17
  18         /* DQ byte map as per doc #573387 */
  19         .lpx_dq_map = {
  20                 .ddr0 = {
  21                         .dq0 = {  3,  0,  2,  1,  4,  6,  5,  7, },
  22                         .dq1 = {  12, 13, 14, 15, 8,  9,  10, 11, },
  23                 },
  24                 .ddr1 = {
  25                         .dq0 = { 13, 14, 11, 12,  10, 8, 15,  9, },
  26                         .dq1 = {  5,  2,  4,  3,  1,  6,  0,  7, },
  27                 },
  28                 .ddr2 = {
  29                         .dq0 = {  2,  3,  1,  0,  7,  6,  5,  4, },
  30                         .dq1 = { 12,  13, 14, 15, 8,  9, 10, 11, },
  31                 },
  32                 .ddr3 = {
  33                         .dq0 = { 13, 14, 12, 15, 11,  9,  8, 10, },
  34                         .dq1 = {  5,  2,  1,  4,  7,  0,  3,  6, },
  35                 },
  36                 .ddr4 = {
  37                         .dq0 = { 11, 10,  8,  9, 14, 15, 13, 12, },
  38                         .dq1 = {  3,  0,  2,  1,  5,  4,  6,  7, },
  39                 },
  40                 .ddr5 = {
  41                         .dq0 = { 11, 15, 13, 12, 10,  9, 14,  8, },
  42                         .dq1 = {  3,  0,  2,  1,  6,  7,  5,  4, },
  43                 },
  44                 .ddr6 = {
  45                         .dq0 = { 11, 13, 10, 12, 15,  9, 14,  8, },
  46                         .dq1 = {  4,  3,  5,  2,  7,  0,  1,  6, },
  47                 },
  48                 .ddr7 = {
  49                         .dq0 = { 12, 13, 15, 14, 11,  9, 10,  8, },
  50                         .dq1 = {  4,  5,  1,  2,  6,  3,  0,  7, },
  51                 },
  52         },
  53
  54         /* DQS CPU<>DRAM map as per doc #573387 */
  55         .lpx_dqs_map = {
  56                 .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
  57                 .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
  58                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
  59                 .ddr3 = { .dqs0 = 1, .dqs1 = 0 },
  60                 .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
  61                 .ddr5 = { .dqs0 = 1, .dqs1 = 0 },
  62                 .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
  63                 .ddr7 = { .dqs0 = 1, .dqs1 = 0 },
  64         },
  65
  66         .LpDdrDqDqsReTraining = 1,
  67
  68         .ect = 1, /* Enable Early Command Training */
  69 };
  70
  71 const struct mb_cfg *variant_memory_params(void)
  72 {
  73         return &baseboard_memcfg;
  74 }
  75
  76 int variant_memory_sku(void)
  77 {
  78         /*
  79          * Memory configuration board straps
  80          * GPIO_MEM_CONFIG_0    GPP_F16
  81          * GPIO_MEM_CONFIG_1    GPP_F12
  82          * GPIO_MEM_CONFIG_2    GPP_F13
  83          * GPIO_MEM_CONFIG_3    GPP_F15
  84          */
  85         gpio_t spd_gpios[] = {
  86                 GPP_F16,
  87                 GPP_F12,
  88                 GPP_F13,
  89                 GPP_F15,
  90         };
  91
  92         return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
  93 }
  94
  95 bool variant_is_half_populated(void)
  96 {
  97         /* GPIO_MEM_CH_SEL GPP_F11 */
  98         return gpio_get(GPP_F11);
  99 }
 100
 101 void variant_get_spd_info(struct mem_spd *spd_info)
 102 {
 103         spd_info->topo = MEM_TOPO_MEMORY_DOWN;
 104         spd_info->cbfs_index = variant_memory_sku();
 105 }