src/mainboard/google/brya/variants/osiris/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/variants.h>
   4 #include <memory_info.h>
   5 #include <string.h>
   6
   7 static const struct mb_cfg osiris_memcfg = {
   8         .type = MEM_TYPE_LP4X,
   9
  10         .rcomp = {
  11                 /* Baseboard uses only 100ohm Rcomp resistors */
  12                 .resistor = 100,
  13
  14                 /* Baseboard Rcomp target values */
  15                 .targets = {40, 30, 30, 30, 30},
  16         },
  17
  18         /* DQ byte map */
  19         .lpx_dq_map = {
  20                 .ddr0 = {
  21                         .dq0 = {  9, 11,  8, 10, 12, 14, 13, 15, },
  22                         .dq1 = {  4,  7,  6,  5,  2,  3,  0,  1, },
  23                 },
  24                 .ddr1 = {
  25                         .dq0 = { 15, 12, 14, 13,  9, 10, 11,  8, },
  26                         .dq1 = {  0,  1,  3,  2,  7,  5,  4,  6, },
  27                 },
  28                 .ddr2 = {
  29                         .dq0 = {  2,  3,  1,  0,  6,  7,  5,  4, },
  30                         .dq1 = { 15,  9, 14,  8, 11, 10, 13, 12, },
  31                 },
  32                 .ddr3 = {
  33                         .dq0 = {  3,  1,  2,  0,  4,  6,  7,  5, },
  34                         .dq1 = { 13, 15, 14, 12, 11,  9,  8, 10, },
  35                 },
  36                 .ddr4 = {
  37                         .dq0 = { 13, 12, 14, 15,  9,  8, 10, 11, },
  38                         .dq1 = {  4,  7,  5,  6,  1,  2,  0,  3, },
  39                 },
  40                 .ddr5 = {
  41                         .dq0 = {  5,  0,  6,  4,  3,  1,  7,  2, },
  42                         .dq1 = { 11,  9, 10,  8, 15, 12, 14, 13, },
  43                 },
  44                 .ddr6 = {
  45                         .dq0 = { 15, 12, 14, 13, 10,  9, 11,  8, },
  46                         .dq1 = {  0,  1,  2,  3,  5,  6,  4,  7, },
  47                 },
  48                 .ddr7 = {
  49                         .dq0 = {  0,  3,  1,  2,  4,  5,  6,  7, },
  50                         .dq1 = { 11,  8, 13, 14,  9, 12, 15, 10, },
  51                 },
  52         },
  53
  54         /* DQS CPU<>DRAM map */
  55         .lpx_dqs_map = {
  56                 .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
  57                 .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
  58                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
  59                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
  60                 .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
  61                 .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
  62                 .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
  63                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
  64         },
  65
  66         .LpDdrDqDqsReTraining = 1,
  67
  68         .ect = 1, /* Enable Early Command Training */
  69 };
  70
  71 static const struct mb_cfg hynix_memcfg = {
  72         .type = MEM_TYPE_LP4X,
  73
  74         .rcomp = {
  75                 /* Baseboard uses only 100ohm Rcomp resistors */
  76                 .resistor = 100,
  77
  78                 /* Baseboard Rcomp target values */
  79                 .targets = {40, 30, 30, 30, 30},
  80         },
  81
  82         /* DQ byte map */
  83         .lpx_dq_map = {
  84                 .ddr0 = {
  85                         .dq0 = {  9, 11,  8, 10, 12, 14, 13, 15, },
  86                         .dq1 = {  4,  7,  6,  5,  2,  3,  0,  1, },
  87                 },
  88                 .ddr1 = {
  89                         .dq0 = { 15, 12, 14, 13,  9, 10, 11,  8, },
  90                         .dq1 = {  0,  1,  3,  2,  7,  5,  4,  6, },
  91                 },
  92                 .ddr2 = {
  93                         .dq0 = {  2,  3,  1,  0,  6,  7,  5,  4, },
  94                         .dq1 = { 15,  9, 14,  8, 11, 10, 13, 12, },
  95                 },
  96                 .ddr3 = {
  97                         .dq0 = {  3,  1,  2,  0,  4,  6,  7,  5, },
  98                         .dq1 = { 13, 15, 14, 12, 11,  9,  8, 10, },
  99                 },
 100                 .ddr4 = {
 101                         .dq0 = { 13, 12, 14, 15,  9,  8, 10, 11, },
 102                         .dq1 = {  4,  7,  5,  6,  1,  2,  0,  3, },
 103                 },
 104                 .ddr5 = {
 105                         .dq0 = {  5,  0,  6,  4,  3,  1,  7,  2, },
 106                         .dq1 = { 11,  9, 10,  8, 15, 12, 14, 13, },
 107                 },
 108                 .ddr6 = {
 109                         .dq0 = { 15, 12, 14, 13, 10,  9, 11,  8, },
 110                         .dq1 = {  0,  1,  2,  3,  5,  6,  4,  7, },
 111                 },
 112                 .ddr7 = {
 113                         .dq0 = {  0,  3,  1,  2,  4,  5,  6,  7, },
 114                         .dq1 = { 11,  8, 13, 14,  9, 12, 15, 10, },
 115                 },
 116         },
 117
 118         /* DQS CPU<>DRAM map */
 119         .lpx_dqs_map = {
 120                 .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
 121                 .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
 122                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
 123                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
 124                 .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
 125                 .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
 126                 .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
 127                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
 128         },
 129
 130         .LpDdrDqDqsReTraining = 1,
 131
 132         .ect = 1, /* Enable Early Command Training */
 133
 134         .cs_pi_start_high_in_ect = 1,
 135 };
 136
 137 const struct mb_cfg *variant_memory_params(void)
 138 {
 139         const char *part_num = mainboard_get_dram_part_num();
 140         const char *hynix_mem1 = "H54G46CYRBX267";
 141         const char *hynix_mem2 = "H54G56CYRBX247";
 142
 143         if (part_num) {
 144                 if (!strcmp(part_num, hynix_mem1) || !strcmp(part_num, hynix_mem2)) {
 145                         printk(BIOS_INFO, "Enable cs_pi_start_high_in_ect for Hynix memory\n");
 146                         return &hynix_memcfg;
 147                 }
 148         }
 149         return &osiris_memcfg;
 150 }